4.9.1. Counter/timer operation

Figure 4.19 shows one counter/timer. Each comprises:

Figure 4.19. Counter/timer block diagram

Timer 0 is clocked by the system bus clock. Timer 1 and Timer 2 are clocked at a fixed frequency of 1MHz. The counters can be clocked directly or with a divide by 16 or 256 clock. The timers provide three operating modes:

Free running

The timer counts down to zero and then wraps around and continues to count down from its maximum value.


The counter counts down to zero and then reloads the period value held in the load register and continues to decrement.

One shot

The counter counts down to zero and does not reload a value.

The prescale divisor and operating modes are selected by programming the control register TIMERx_CTRL.

The timer is enabled by setting a bit in the TIMERx_CTRL register. This register also contains the prescale selection bits and mode control bit.

A timer is loaded by writing to the load register TIMERx_LOAD. If the timer is enabled it begins a down count. When it reaches zero it generates an interrupt request. Interrupts are cleared by writing to the TIMERx_CLR register. The current value can be read at any time from the TIMERx_VALUE register.

For the one-shot mode, the counter generates an interrupt once only. When the counter reaches zero, it halts until reprogrammed by the user. This can be achieved by either clearing the One Shot Count bit in the control register (in which case the count will proceed according to the selection of Free-running or Periodic mode), or by writing a new value to the Load Value register.

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