4.8.3. UART interrupts

Each UART generates four interrupts. These are:

Modem status interrupt

This is asserted when any of the status lines (DCD, DSR, and CTS) change. It is cleared by writing to the UART_ICR register.

UART disabled interrupt

This is asserted when the UART is disabled and a start bit (low level) is detected on the receive line. It is cleared if the UART is enabled or if the receive line goes HIGH.

Rx interrupt

This is asserted when one of the following events occur:

  • the receive FIFO is enabled and the FIFO is half or more than half full (contains eight or more bytes)

  • the receive FIFO is not empty and there has been no data for more than a 32-bit period

  • the receive FIFO is disabled and data is received.

The Rx interrupt is cleared by reading contents of the FIFO.

Tx interrupt

This is asserted when one of the following events occur:

  • the transmit FIFO is enabled and the FIFO is half or less than half full

  • the transmit FIFO is disabled and the holding buffer is empty.

The Tx interrupt is cleared by filling the FIFO to more than half full or writing to the holding register.

Copyright © 2002 ARM Limited. All rights reserved.ARM DUI 0159B
Non-Confidential