B.1.2. Baseboard connector HDRB

Figure B.2 shows the pin numbers of the connector HDRB on the baseboard.

Figure B.2. HDRB pin numbering

Table B.2 describes the signals on the pins labeled E[31:0], F[31:0], and G[16:0] for AMBA AHB-Lite system bus. The signal names are the standard AHB names. Some pins have different functions under AHB-Lite or when used on the Integrator/CP.

Table B.2. HDRB signal description

Pin label

Signal NameCP specific

Description

E[31:28]

HCLK[3:0]

-

System clock to the core module.

E[27:24]

nPPRES[3:0]

Yes

Core Module present.

Each core module ties nPPRES[0] LOW and leaves nPPRES[3:1] open circuit. These signals rotate as they move up or down the stack so that there is a connection between each module and one of these signals at the system controller on the baseboard. Only one core module however, is permitted in the Integrator/CP system.

E[23:20]

nIRQ[3:0]

-

Interrupt request to processor.

E[19:16]

nFIQ[3:0]

-

Fast interrupt requests to processor.

E[15:12]

ID[3:0]

Yes

Core Module stack position indicator. Only one core module however, is permitted in the Integrator/CP system.

E[11:8]

HLOCK[3:0]Yes

System bus lock from processor, but only a single core module is permitted.

E[7:4]

HGRANT[3:0]

Yes

System bus grant to processor, but only a single core module is permitted.

E[3:0]

HBUSREQ[3:0]

Yes

System bus request from processor, but only a single core module is permitted.

F[31:16] and F[9:8]

-

YesA variety of interface connections

F[15:10]

-

YesMMC interface signals
F[13] and F[7:5]

-

YesAudio codec signal

F[4:0]

-

YesTouchscreen host interface signals

G16

nRTCKEN

-

RTCK AND gate enable.

G[15:14]

CFGSEL[1:0]

-

FPGA configuration select.

G13

nCFGEN

-

Sets system into configuration mode.

G12

nSRST

-

Multi-ICE reset (open collector).

G11

FPGADONE

-

Indicates when FPGA configuration is complete.

G10

RTCK

-

Returned JTAG test clock.

G9

nSYSRST

-

Buffered system reset.

G8

nTRST

-

JTAG reset.

G7

TDO

-

JTAG test data out.

G6

TDI

-

JTAG test data in.

G5

TMS

-

JTAG test mode select.

G4

TCK

-

JTAG test clock.

G[3:1]

HMAST[2:0]

Yes

Master ID. Binary encoding of the master currently performing a transfer on the bus. Corresponds to the module ID and to the HBUSREQ and HGRANT line numbers.

However on AHB-Lite, only one master is permitted.

G0

nMBDET

-

Baseboard detect. This signal is tied LOW on the CP.

When a module is attached to the baseboard, it detects that nMBDET is LOW and routes TDI and TCK down to the baseboard where they are looped back onto TDO and RTCK. Also, core modules pass addresses above 0x11000000 on to the system bus where they are decoded by the baseboard or by other modules. For the Integrator/CP, however, one core module is permitted.

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