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| Home > Peripherals and Interfaces > UART interface > Overview of UART registers | |||
The UART registers are listed in Table 4.17. For more detailed information, refer to the ARM PrimeCell UART (PL011) Technical Reference Manual. The base addresses for the UARTs are:
0x16000000UART0, the top port on the connector, also called serial A.
0x17000000UART1, the bottom port on the connector, also called serial B.
Table 4.17. UART register summary
Address (UART 0)[1] | Type | Width | Reset value | Name | Description |
|---|---|---|---|---|---|
| Read/write | 12/8 |
| UARTDR | Data read or written from the interface. It is 12 bits wide on a read, and 8 on a write. This is also the UART base address. |
| Read/write | 4/0 |
| UARTRSR/ UARTECR | Receive status register (read)/ error clear register (write). |
| - | - | - | - | Reserved. |
| Read | 9 |
| UARTFR | Flag register (read only). |
| - | - | - | - | Reserved. |
| Read/write | 8 |
| UARTILPR | IrDA low-power counter register. |
| Read/write | 16 |
| UARTIBRD | Integer baud rate divisor register. |
| Read/write | 6 |
| UARTFBRD | Fractional baud rate divisor register. |
| Read/write | 8 |
| UARTLCR_H | Line control register, HIGH byte. |
| Read/write | 16 |
| UARTCR | Control register. |
| Read/write | 6 |
| UARTIFLS | Interrupt FIFO level select register. |
| Read/write | 11 |
| UARTIMSC | Interrupt mask set/clear. |
| Read | 11 |
| UARTRIS | Raw interrupt status. |
| Read | 11 |
| UARTMIS | Masked interrupt status. |
| Write | 11 | - | UARTICR | Interrupt clear register. |
| Read/write | 3 |
| UARTDMACR | DMA control register. |
| - | - | - | - | Reserved. |
| - | - | - | - | Reserved (for test purposes). |
| - | - | - | - | Reserved. |
| - | - | - | - | Reserved for future ID expansion. |
| Read | 8 |
| UARTPeriphID0 | Peripheral identification register bits [7:0]. |
| Read | 8 |
| UARTPeriphID1 | Peripheral identification register bits [15:8]. |
| Read | 8 |
| UARTPeriphID2 | Peripheral identification register bits [23:16]. |
| Read | 8 |
| UARTPeriphID3 | Peripheral identification register bits [31:24]. |
| Read | 8 |
| UARTPCellID0 | PrimeCell identification register bits [7:0]. |
| Read | 8 |
| UARTPCellID1 | PrimeCell identification register bits [15:8]. |
| Read | 8 |
| UARTPCellID2 | PrimeCell identification register bits [23:16]. |
| Read | 8 |
| UARTPCellID3 | PrimeCell identification register bits [31:24]. |
[1] For UART
1, use | |||||