Integrator®/CP User Guide 4.9.2. Counter/timer registers

4.9.2. Counter/timer registers

The counter/timer registers control the three counter/timers. There are seven registers for each of the counter/timers, as shown in Table 4.18.

Table 4.18. Timer register summary

Address	Type	Width	Reset value	Name	Description
`0x13000000`	Read/write	32	`0x00000000`	Timer0Load	Load value for Timer 0
`0x13000004`	Read	32	`0xFFFFFFFF`	Timer0Value	The current value for Timer 0
`0x13000008`	Read/write	8	`0x20`	Timer0Control	Timer 0 control register
`0x1300000C`	Write	-	-	Timer0IntClr	Timer 0 interrupt clear
`0x13000010`	Read	1	`0x0`	Timer0RIS	Timer 0 raw interrupt status
`0x13000014`	Read	1	`0x0`	Timer0MIS	Timer 0 masked interrupt status
`0x13000018`	Read/write	32	`0x00000000`	Timer0BGLoad	Background load value for Timer 0
`0x13000100`	Read/write	32	`0x00000000`	Timer1Load	Load value for Timer 1
`0x13000104`	Read	32	`0xFFFFFFFF`	Timer1Value	The current value for Timer 1
`0x13000108`	Read/write	8	`0x20`	Timer1Control	Timer 1 control register
`0x1300010C`	Write	-	-	Timer1IntClr	Timer 1 interrupt clear
`0x13000110`	Read	1	`0x0`	Timer1RIS	Timer 1 raw interrupt status
`0x13000114`	Read	1	`0x0`	Timer1MIS	Timer 1 masked interrupt status
`0x13000118`	Read/write	32	`0x00000000`	Timer1BGLoad	Background load value for Timer 1
`0x13000200`	Read/write	32	`0x00000000`	Timer2Load	Load value for Timer 2
`0x13000204`	Read	32	`0xFFFFFFFF`	Timer2Value	The current value for Timer 2
`0x13000208`	Read/write	8	`0x20`	Timer2Control	Timer 2 control register
`0x1300020C`	Write	-	-	Timer2IntClr	Timer 2 interrupt clear
`0x13000210`	Read	1	`0x0`	Timer2RIS	Timer 2 raw interrupt status
`0x13000214`	Read	1	`0x0`	Timer2MIS	Timer 2 masked interrupt status
`0x13000218`	Read/write	32	`0x00000000`	Timer2BGLoad	Background load value for Timer 2

Timer x load register

This is a 32-bit register containing the value from which the counter is to decrement. This is the value used to re-load the counter when Periodic mode is enabled, and the current count reaches zero.

When this register is written to directly, the current count is immediately reset to the new value at the next rising edge of TIMCLK which is enabled by TIMCLKEN.

The value in this register is also overwritten if the TimerXBGLoad register is written to, but the current count is not immediately affected.

If values are written to both the TimerXLoad and TimerXBGLoad registers before an enabled rising edge on TIMCLK, the following occurs:

on the next enabled TIMCLK edge, the value written to the TimerXLoad value replaces the current count value
each time the counter reaches zero, the current count value is reset to the value written to TimerXBGLoad.

Reading from the TimerXLoad register at any time after the two writes have occurred will retrieve the value written to TimerXBGLoad. That is, the value read from TimerXLoad is always the value that will take effect for Periodic mode after the next time the counter reaches zero.

Timer x background load

This is a 32-bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero.This register provides an alternative method of accessing the TimerXLoad register. The difference is that writes to TimerXBGLoad will not cause the counter immediately to restart from the new value.Reading from this register returns the same value returned from TimerXLoad.

Timer x current value register

The timer value register contains the current count value for the timer. The upper 16 bits (of 32 bits) are undefined.

Timer x control register

The timer control registers are 8-bit read/write registers that control the operation of their associated counter/timers. The format of these three registers is similar.

Figure 4.20. Timer control register

Table 4.19 describes the timer control register bits.

Table 4.19. TIMERx_CTL register

Bit	Name	Function
[7]	ENABLE	Timer enable: 0 = disabled 1 = enabled.
[6]	MODE	Timer mode: 0 = free running, counts once and then wraps to `0xFFFF` 1 = periodic, reloads from load register at the end of each count.
[5]	IE	Interrupt enable
[4]	R	Unused, always write as 0s.
3:2	PRESCALE	Prescale divisor: 00 = none 01 = divide by 16 10 = divide by 256 11 = undefined.
1	TimerSize	Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0.
0	OneShot Count	Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode

Timer x clear register

The timer clear register is a write-only location that does not have a storage element. Writing any value to this location clears the interrupt for the associated counter/timer.

Timer x raw interrupt status register

Bit 0 of this register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the control register to create the masked interrupt that is passed to the interrupt output pin. Table 4.20 shows the bit assignments for the TimerXRIS register.

Table 4.20. TimerXRIS register

Bit	Name	Type	Function
[0]	Raw Timer Interrupt	Read	Raw interrupt status from the counter

Timer x interrupt status register

Bit 0 of this register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the timer interrupt enable bit from the control register, and is the same value that is passed to the interrupt output pin. Table 4.21 shows the bit assignments for the TimerXMIS register.

Table 4.21. TimerXMIS register

Bit	Name	Type	Function
[0]	Timer Interrupt	Read	Enabled interrupt status from the counter

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