B.1.1. Baseboard connector HDRA

Figure B.1 shows the pin numbering of the connector HDRA on the baseboard.

Figure B.1. Connector pin numbering

The signals on the pins labeled A[31:0], B[31:0], C[31:0], and D[31:0] are listed in Table B.1. A more in depth description of these buses in provided in Baseboard AHB bus. The signal names are the standard AHB names. Some pins have different functions under AHB-Lite or when used on the Integrator/CP.

Table B.1. HDRA signals descriptions

Pin label

AHB signal nameCP specific[1]

Description

A[31:0]

HADDR[31:0]-

System address bus

B[31:0]

Peripheral controlYesPeripheral connections between base board and core module

C[31:16]

Peripheral controlYesPeripheral connections between base board and core module

C15

ReservedYes

Locked transaction

On AHB-Lite there is only one master, therefore arbitration is not required.

C14ReservedYesNot used on Integrator/CP core modules

C13

HRESP0-

Slave response

C12

HREADY

-

Slave wait response

C11

HWRITE

-

Write transaction

C10

HPROT2

-

Transaction protection type

C[9:8]

HPROT[1:0]

-

Transaction protection type

C[7:5]

HBURST[2:0]

-

Transaction burst size

C4HPROT[3]-

Transaction protection type

C[3:2]

HSIZE[1:0]

-

Transaction width

The AHB specification defines a 3-bit bus for HSIZE, but 2 bits is sufficient to describe transfers of up to 64-bits wide which is why a 2-bit bus is sufficient on Integrator.

C[1:0]

HTRAN[1:0]

-

Transaction type

D[31:0]

HDATA[31:0]-

System data bus

[1] The use of these pins is specific to the Integrator/CP and might not be compatible with other modules that use this pins for other functions.

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