3.6.4. Handling interrupts

This section describes interrupt handling and clearing in general. For examples of interrupt detection and handling, see the ARM Firmware Suite User Guide, the ARM Developer Suite Developer Guide, and the documentation supplied with your core module.

Enabling IRQ interrupts

The majority of peripheral interrupts are routed direct to the PIC. Each peripheral contains its own interrupt mask and clear registers. To enable interrupts, you must clear both the peripheral interrupt mask and the interrupt controller mask as well as clearing any previous interrupt flags:

  1. Disable the primary interrupt by setting the appropriate bit in PIC_IRQ_ENCLR.

  2. Clear the peripheral interrupt by setting the appropriate bit in the peripheral interrupt clear register.

  3. Unmask the peripheral interrupt by clearing the appropriate bit in peripheral interrupt mask register.

  4. Enable the primary interrupt by setting the appropriate bit in PIC_IRQ_ENSET.

The following C code stub demonstrates how the PIC UART0 CTS interrupt is cleared and re-enabled:

*PIC_IRQ_ENCLR    = PIC_UARTINT0;
*UART0_UARTICR    = UART_CTSINTR;
*UART0_UARTIMSC   &= ~UART_CTSINTR;
*PIC_IRQ_ENSET    |= PIC_UARTINT0;

The following C code stub demonstrates how the SIC MMCI CARDIN is cleared and re-enabled:

*PIC_IRQ_ENCLR   = PIC_CPPLDINT;
*CP_INTREG 	      = SIC_CARDIN;
*SIC_IRQ_ENSET   |= SIC_CARDIN;
*PIC_IRQ_ENSET   |= PIC_ CPPLDINT;

Note

The constants in these C code stubs must contain bit patterns necessary to set only the required interrupt mask bits. For example, PIC_UARTINT0 must contain 0x02 to set only the UART0 bit in the PIC_IRQ_ENCLR register.

Determining and clearing IRQ interrupts

To determine an interrupt source, read the STATUS registers in the PIC and CIC to determine the interrupt controller that generated the interrupt. The sequence to determine and clear the interrupt is:

  1. Determine the interrupt source by reading CM_IRQ_STATUS and PIC_STATUS.

    The interrupt handler is directed by the status register information to the particular peripheral that generated the interrupt. In the case of SIC interrupts the interrupt handler must also read the SIC STATUS register to determine the interrupt source.

  2. Determine the peripheral interrupt source by reading the peripheral masked interrupt status register.

  3. Clear the peripheral interrupt by setting the appropriate bit in the peripheral interrupt clear register.

The following pseudo code example demonstrates how the UART0 CTS interrupt is detected:

If CM_IRQ_STATUS flags set,
      . . .  CIC interrupt handler

If PIC_STATUS flags set, 
      . . . PIC interrupt handler
     If PIC_CPPLDINT set,
           . . .  SIC interrupt handler
     If PIC_UARTINT0 set,
           . . . UART0 interrupt handler
           If UART0_UARTMIS, UART_CTSINTR flag set,
                   . . . act on interrupt then clear flag with UARTICR
     . . . Test other PIC flags
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