4.2.1. About the SMSC LAN91C111

The SMCS LAN91C11 is a fast Ethernet controller that incorporates a Media ACcess (MAC) Layer, a PHYsical address (PHY) layer, and an 8KB dynamically configurable transmit and receive FIFO SRAM.

The controller supports dual-speed 100Mbps or 10Mbps and autoconfiguration. When autoconfiguration is enabled, the chip is automatically configured for network speed and for full or half-duplex operation.

The controller uses a local VL-Bus host interface with a bridge to the AHB Lite bus provided by the PLD. The PLD generates the appropriate access control signals for the host side of the Ethernet controller. The VL-Bus is a synchronous bus that supports 32-bit accesses.

The internal registers occupy 16 word locations. These are organized into four banks of 8 x 16-bit registers located at 0xC8000000 in the Integrator/CP memory map. Table 4.2 lists the internal registers.

Table 4.2. LAN91C111 internal registers

OffsetBank 0Bank 1Bank 2Bank 3

The LAN91C111 is a little-endian device. The default configuration for the system bus is also little-endian. If you configure the system bus for big-endian operation you must perform word and byte swapping in software.

A serial EEPROM provides parameters to the LAN91C111 at reset. These parameters are:

When manufactured, an ARM value for the Ethernet MAC address and the register base address are loaded into the EEPROM. The register base address is 0. The MAC address is unique, but can be reprogrammed if desired. Reprogramming of the EEPROM is done through Bank 1 (general and control registers).

To access the PHY MII registers, you must implement a synchronous serial connection in software to control the management register in Bank 3. By default, the PHY is set to isolate in the control register. This disables the external interface. Refer to the LAN91C111 application note or to the self test program for additional information.

The LAN91C111 is provided with a 25MHz reference clock.

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