4.3.6. Color LCD registers

This section describes the color LCD registers, for more detail see the PrimeCell Color LCD controller (PL110).

The following locations are reserved, and must not be used during normal operation:

The PrimeCell CLCDC registers are shown in Table 4.4.

Table 4.4. PrimeCell CLCDC register summary

Address

Type

Width

Reset

value

Name

Description

0xC0000000

Read/write

32

0

LCDTiming0

Horizontal axis panel control

0xC0000004

Read/write

32

0

LCDTiming1

Vertical axis panel control

0xC0000008

Read/write

27

0

LCDTiming2

Clock and signal polarity control

0xC000000C

Read/write

17

0

LCDTiming3

Line end control

0xC0000010

Read/write

32

0

LCDUPBASE

Upper panel frame base address

0xC0000014

Read/write

32

0

LCDLPBASE

Lower panel frame base address

0xC0000018

Read/write

5

0

LCDINTRENABLE

Interrupt enable mask

0xC000001C

Read/write

16

0

LCDControl

LCD panel pixel parameters

0xC0000020

Read/write

5

0

LCDStatus

Raw interrupt status

0xC0000024

Read

5

0

LCDInterrupt

Final masked interrupts

0xC0000028

Read

32

X

LCDUPCURR

LCD upper panel current address value

0xC000002C

Read

32

X

LCDLPCURR

LCD lower panel current address value

0xC0000030 – 0xC00001FC

-

-

-

-

Reserved

0xC0000200 - 0xC00003FC

Read/write

32

-

LCDPalette

256 x 16-bit color palette

For VGA operation, perform the steps below and set the register values as shown in Table 4.5.

Table 4.5. Register values for VGA operation

Step number Address ValueDescription
10x100000140xa05FWrite this value to the CM_LOCK register to enable changing the clock rate.
20x1000001C0x12C11Set AUXCLK (pixel clock) to 25MHz. This is the default value for AUXCLK.
30xC00000000x3F1F3F9CSet the horizontal timing value in LCD_TIM0.
40xC00000040x080B61DFSet the vertical timing value in LCD_TIM1.
50xC00000080x067F3800Set other timing values in LCD_TIM2.
60xC0000010 FRAMEBASESet up the base address for the LCD frame buffer to, for example, 0x200000.
70xC000001C0x1821 0x1823 0x1825 0x1827 0x1829 0x182B Sets the bits per pixel: 1  2 4  8  16 24
80x1000000C 0x3e005 for 1,2,4,8, or 16 bits per pixel modes 0x33805 for 24 bits per pixel modeSet the output multiplexor value in the CM_CTRL register to drive the VGA interface. Use read-modify-write to preserve the values of other bits (for example, REMAP) in the CM_CTRL register.
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