Integrator®/CP User Guide 4.3.6. Color LCD registers

This section describes the color LCD registers, for more detail see the PrimeCell Color LCD controller (PL110).

The following locations are reserved, and must not be used during normal operation:

locations 0xC0000030 through 0xC00001FC are reserved for possible future extensions
locations at offsets 0xC0000400 through 0xC00007FF are reserved for test purposes.

The PrimeCell CLCDC registers are shown in Table 4.4.

Table 4.4. PrimeCell CLCDC register summary

Address	Type	Width	Reset value	Name	Description
`0xC0000000`	Read/write	32	`0`	LCDTiming0	Horizontal axis panel control
`0xC0000004`	Read/write	32	`0`	LCDTiming1	Vertical axis panel control
`0xC0000008`	Read/write	27	`0`	LCDTiming2	Clock and signal polarity control
`0xC000000C`	Read/write	17	`0`	LCDTiming3	Line end control
`0xC0000010`	Read/write	32	`0`	LCDUPBASE	Upper panel frame base address
`0xC0000014`	Read/write	32	`0`	LCDLPBASE	Lower panel frame base address
`0xC0000018`	Read/write	5	`0`	LCDINTRENABLE	Interrupt enable mask
`0xC000001C`	Read/write	16	`0`	LCDControl	LCD panel pixel parameters
`0xC0000020`	Read/write	5	`0`	LCDStatus	Raw interrupt status
`0xC0000024`	Read	5	`0`	LCDInterrupt	Final masked interrupts
`0xC0000028`	Read	32	X	LCDUPCURR	LCD upper panel current address value
`0xC000002C`	Read	32	X	LCDLPCURR	LCD lower panel current address value
`0xC0000030 – 0xC00001FC`	-	-	-	-	Reserved
`0xC0000200 - 0xC00003FC`	Read/write	32	-	LCDPalette	256 x 16-bit color palette

For VGA operation, perform the steps below and set the register values as shown in Table 4.5.

Table 4.5. Register values for VGA operation

Step number	Address	Value	Description
1	`0x10000014`	`0xa05F`	Write this value to the CM_LOCK register to enable changing the clock rate.
2	`0x1000001C`	`0x12C11`	Set AUXCLK (pixel clock) to 25MHz. This is the default value for AUXCLK.
3	`0xC0000000`	`0x3F1F3F9C`	Set the horizontal timing value in LCD_TIM0.
4	`0xC0000004`	`0x080B61DF`	Set the vertical timing value in LCD_TIM1.
5	`0xC0000008`	`0x067F3800`	Set other timing values in LCD_TIM2.
6	`0xC0000010`	`FRAMEBASE`	Set up the base address for the LCD frame buffer to, for example, `0x200000`.
7	`0xC000001C`	`0x1821` `0x1823` `0x1825` `0x1827` `0x1829` `0x182B`	Sets the bits per pixel: 1 2 4 8 16 24
8	`0x1000000C`	`0x3e005` for 1,2,4,8, or 16 bits per pixel modes `0x33805` for 24 bits per pixel mode	Set the output multiplexor value in the CM_CTRL register to drive the VGA interface. Use read-modify-write to preserve the values of other bits (for example, REMAP) in the CM_CTRL register.

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