Integrator™/CM10200E and CM10220E User Guide 4.3. Registers

4.3. Registers

The core module status and control registers enable the processor to determine its environment and to control some core module operations. The registers, listed in Table 4.4, are located at 0x10000000 and can only be accessed by the local processor.

Table 4.4. Core module registers

Register name	Address	Access	Reset	Description
CM_ID	`0x10000000`	Read	Static	See ID Register, CM_ID
CM_PROC	`0x10000004`	Read	Static	See Processor Register, CM_PROC
CM_OSC	`0x10000008`	Read/write	POR	See Oscillator Register, CM_OSC
CM_CTRL	`0x1000000C`	Read/write	Reset	See Control Register, CM_CTRL
CM_STAT	`0x10000010`	Read	Reset	See Status Register, CM_STAT
CM_LOCK	`0x10000014`	Read/write	Reset	See Lock Register, CM_LOCK
CM_LMBUSCNT	`0x10000018`	Read	Reset	See Local Memory Bus Cycle Counter, CM_LMBUSCNT
CM_AUXOSC	`0x1000001C`	Read/write	POR	See Auxiliary Oscillator Register, CM_AUXOSC
CM_SDRAM	`0x10000020`	Read/write	POR	See SDRAM Status and Control Register, CM_SDRAM
CM_INIT	`0x10000024`	Read/write	POR	See Core Module Initialization Register, CM_INIT
CM_REFCNT	`0x10000028`	Read	Reset	See Reference Clock Cycle Counter Register, CM_REFCNT
CM_UNUSED1	`0x1000002C`	-	-	Reserved
CM_FLAGS	`0x10000030`	Read	Reset	See Flag and Nonvolatile Flag Register
CM_FLAGSET	`0x10000030`	Write	Reset	See Flag and Nonvolatile Flag Set Register
CM_FLAGSCLR	`0x10000034`	Write	Reset	See Flag and Nonvolatile Flag Clear Register
CM_NVFLAGS	`0x10000038`	Read	POR	See Flag and Nonvolatile Flag Register
CM_NVFLAGSSET	`0x10000038`	Write	POR	See Flag and Nonvolatile Flag Set Register
CM_NVFLAGSCLR	`0x1000003C`	Write	POR	See Flag and Nonvolatile Flag Clear Register
CM_IRQ_STATUS	`0x10000040`	Read	Reset	See IRQ Status and FIQ Status Registers
CM_IRQ_RSTAT	`0x10000044`	Read	Reset	See IRQ Raw Status and FIQ Raw Status Registers
CM_IRQ_ENSET	`0x10000048`	Read	Reset	See IRQ Enable Set and FIQ Enable Set Registers
CM_IRQ_ENCLR	`0x1000004C`	Write	Reset	See IRQ Enable Clear and FIQ Enable Clear Registers
CM_SOFT_INTSET	`0x10000050`	Read/write	Reset	See Soft Interrupt Set and Soft Interrupt Clear Registers
CM_SOFT_INTCLR	`0x10000054`	Write	Reset	See Soft Interrupt Set and Soft Interrupt Clear Registers
CM_FIQ_STATUS	`0x10000060`	Read	Reset	See IRQ Status and FIQ Status Registers
CM_FIQ_RSTAT	`0x10000064`	Read	Reset	See IRQ Raw Status and FIQ Raw Status Registers
CM_FIQ_ENSET	`0x10000068`	Read/write	Reset	See IRQ Enable Set and FIQ Enable Set Registers
CM_FIQ_ENCLR	`0x1000006C`	Write	Reset	See IRQ Enable Set and FIQ Enable Set Registers
CM_VOLTAGE_CTL0	`0x10000080`	Read/write	Reset	See Core Module Voltage Configuration Registers, CM_VOLTAGE_CTL0-3
CM_VOLTAGE_CTL1	`0x10000084`	Read/write	Reset	See Core Module Voltage Configuration Registers, CM_VOLTAGE_CTL0-3
CM_VOLTAGE_CTL2	`0x10000088`	Read/write	Reset	See Core Module Voltage Configuration Registers, CM_VOLTAGE_CTL0-3
CM_VOLTAGE_CTL3	`0x1000008C`	Read/write	Reset	See Core Module Voltage Configuration Registers, CM_VOLTAGE_CTL0-3
CM_SPD	`0x10000100`- `0x100001FC`	Read	POR	See SDRAM SPD memory

Note

All registers are 32-bits wide and do not support byte writes. Write operations must be word-wide. Bits marked as reserved in the following sections must be preserved using read-modify-write operations.

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