Integrator™/CM10200E and CM10220E User Guide 4.3.14. Interrupt control registers

4.3.14. Interrupt control registers

The core module provides a 3-bit IRQ controller and 3-bit FIQ controller to support the debug communications channel used for passing information between applications software and the debugger. See Interrupt control for more information on using the core module with an Integrator/AP motherboard.

The interrupt control registers are listed in Table 4.18.

Table 4.18. Interrupt control registers

Register name	Address	Access	Description
CM_IRQ_STAT	`0x10000040`	Read	core module IRQ Status register
CM_IRQ_RSTAT	`0x10000044`	Read	core module IRQ Raw Status register
CM_IRQ_ENSET	`0x10000048`	Read/write	core module IRQ Enable Set register
CM_IRQ_ENCLR	`0x1000004C`	Write	core module IRQ Enable Clear register
CM_SOFT_INTSET	`0x10000050`	Read/write	core module software interrupt set
CM_SOFT_INTCLR	`0x10000054`	Write	core module software interrupt clear
CM_FIQ_STAT	`0x10000060`	Read	core module FIQ Status register
CM_FIQ_RSTAT	`0x10000064`	Read	core module FIQ Raw Status register
CM_FIQ_ENSET	`0x10000068`	Read/write	core module FIQ Enable Set register
CM_FIQ_ENCLR	`0x1000006C`	Write	core module FIR Enable Clear register

Note

All registers are 32 bits wide and do not support byte writes. Write operations must be word-wide. The values of bits marked as reserved in the interrupt controller registers must be written as 0s.

The IRQ and FIQ controllers each provide three registers for controlling and handling interrupts. These are:

status register
raw status register
enable register (read the current value from CM_IRQ_ENSET and CM_FIQ_ENSET).

The way that the interrupt enable, clear, and status bits function for each interrupt is shown in Figure 4.12 and described in the following subsections. The illustration shows the control for one IRQ bit. The remaining IRQ bits and FIQ bits are controlled in a similar way.

Figure 4.12. Interrupt control

IRQ Status and FIQ Status Registers

The Status Register contains the logical AND of the bits in the Raw Status Register and the Enable Register.

IRQ Raw Status and FIQ Raw Status Registers

The Raw Status Register indicates the signal levels on the interrupt request inputs. A bit set to 1 indicates that the corresponding interrupt request is active.

IRQ Enable Set and FIQ Enable Set Registers

Use the Enable Set Registers to enable interrupts:

write 1 to SET the associated bit and enable the interrupt
write 0 to leave the associated bit unchanged.

Read the current state of the enable bits from the Enable Set Registers.

IRQ Enable Clear and FIQ Enable Clear Registers

Use the Enable Clear Registers to disable interrupts as follows:

write 1 to CLEAR the associated bit and disable the interrupt
write 0 to leave the associated bit unchanged.

Interrupt register bit assignments

The bit assignments for the IRQ and FIQ Status, Raw Status, Enable registers are shown in Figure 4.13 and Table 4.19.

Figure 4.13. IRQ and FIQ bit assignments

Table 4.19. IRQ and FIQ register bit assignment

Bit	Name	Function
[31:3]	Reserved	Write 0 to these bits.
[2]	COMMTx	Debug communications transmit interrupt. This interrupt indicates that the communications channel is available for the processor to pass messages to the debugger.
[1]	COMMRx	Debug communications receive interrupt. This interrupt indicates to the processor that messages are available for the processor to read.
[0]	SOFT	Software interrupt. Enabling and disabling the software interrupt is done with the Enable Set and Enable Clear Registers. Triggering the interrupt however, is done from the Soft Interrupt Set register.

Soft Interrupt Set and Soft Interrupt Clear Registers

The core module interrupt controller provides a register for controlling and clearing software interrupts. This register is accessed using CM_SOFT_INTSET and CM_SOFT_INTCLR:

Set the software interrupt by writing to the CM_SOFT_INTSET register at 0x10000050:
- write a 1 to SET the software interrupt
- write a 0 to leave the software interrupt unchanged.
Read the current state of the of the Software Interrupt Register from the CM_SOFT_INTSET location at 0x10000050. A 1 indicates that the interrupt request is active.
Clear the software interrupt by writing to the CM_SOFT_INTCLR register at 0x10000054:
- write a 1 to CLEAR the software interrupt
- write a 0 to leave the software interrupt unchanged.

Note

Enabling and disabling the software interrupt is done through the IRQ and FIQ registers (see IRQ Enable Set and FIQ Enable Set Registers).

The bit assignment for the software interrupt register is shown in Table 4.20.

Table 4.20. IRQ register bit assignment

Bit	Name	Function
[31:1]	Reserved	Write as 0. Reads undefined.
[0]	SOFT	Software interrupt.

Note

The software interrupt described in this section is used by software to generate IRQs or FIQs. Do not confuse it with the ARM SWI software interrupt instruction. See the ARM Architecture Reference Manual.

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