Integrator™/CM10200E and CM10220E User Guide 3.4.3. JTAG connection modes

3.4.3. JTAG connection modes

The core module is capable of operating in:

Normal debug mode

During normal operation and software development, the core module operates in debug mode. The debug mode is selected by default (when a jumper is not fitted at the CONFIG link, see Figure 3.12). In this mode, the processor core and debuggable devices on other modules are accessible on the scan chain, as shown in Figure 3.13.

Configuration mode

In configuration mode the debuggable devices are still accessible and, in addition, all FPGAs and PLDs in the system are added into the scan chain. This enables the board to be configured or upgraded in the field using Multi-ICE or other JTAG debugging equipment.

To select configuration mode, fit a jumper to the CONFIG link on the core module at the top of the stack (see Figure 3.12). This has the effect of pulling the nCFGEN signal LOW. nCFGEN illuminates the CFG LED on each module in the stack and reroutes the JTAG scan path. The LED provides a warning that the development system is in the configuration mode.

Note

Configuration mode is guaranteed for a single core module attached to a motherboard but might be unreliable if more than one core module is attached. The larger loads on the TCK and TMS lines can cause unreliable operation.

After configuration or code updates you must:

Remove the CONFIG link.
Power cycle the development system.

The configuration mode enables FPGA and PLD code to be updated as follows:

The FPGAs are volatile, but load their configuration from flash memory. Flash memory does not have a JTAG port, but it can be programmed by loading designs into the FPGAs and PLDs using JTAG. These devices transfer the data from the JTAG programming utility to the flash.
The PLDs are nonvolatile devices that can be programmed directly by JTAG.

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