Integrator ™/CM10200Eand CM10220E User Guide


Table of Contents

About this document
Intended audience
Typographical conventions
Further reading
Feedback on the ARM Integrator/CM10200Eand CM10220E
Feedback on this document
1. Introduction
1.1. About the core module
1.2. Core module architecture
1.2.1. System architecture
1.2.2. ARM processor test chip
1.2.3. Core module FPGA
1.2.4. Volatile memory
1.2.5. Clock generator
1.2.6. Multi-ICE ® connector
1.2.7. Test chip power supplies
1.2.8. Logic analyzer and trace connectors
1.3. Links and indicators
1.3.1. CFGEN link
1.3.2. LED indicators
1.4. Test points
1.5. Precautions
1.5.1. Ensuring safety
1.5.2. Preventing damage
2. Getting Started
2.1. Setting up a standalone core module
2.1.1. Fitting an SDRAM DIMM
2.1.2. Using the core module without an external SDRAM DIMM
2.1.3. Supplying power
2.1.4. Connecting Multi-ICE
2.2. Attaching the core module to a motherboard
2.2.1. Core module ID
2.2.2. Powering the assembled Integrator development system
3. Hardware Description
3.1. ARM microprocessor test chip
3.1.1. ARM10200E reference device overview
3.1.2. Test chip configuration control
3.1.3. Fixed value test chip configurationcontrol
3.2. Core module FPGA
3.2.1. SDRAM DIMM controller
3.2.2. SSRAM Controller
3.2.3. Reset and power-management controller
3.2.4. Control of core and cache voltages
3.2.5. Debug communicationsinterrupts
3.3. Clock generators
3.3.1. Clock generation functional overview
3.3.2. Programming the processor clock (PLLCLK)
3.3.3. Programming the auxiliary clock (AUXCLK)
3.3.4. Programming the output dividers
3.3.5. FPGA reference clock (CLKREF24MHZ)
3.4. Multi-ICE support
3.4.1. Multi-ICE connection
3.4.2. JTAG scan paths
3.4.3. JTAG connection modes
3.4.4. JTAG signals
3.5. Embedded Trace support
3.5.1. About using trace
3.5.2. Core trace configuration
3.5.3. Trace interface description
3.6. Stacking options
4. Programmer’s Reference
4.1. Memory organization
4.1.1. Core module memory map
4.1.2. Using REMAP
4.1.3. SDRAM DIMM mapping
4.1.4. Global SDRAM access
4.1.5. Private SDRAM configuration
4.2. Exception vector mapping
4.3. Registers
4.3.1. ID Register, CM_ID
4.3.2. Processor Register, CM_PROC
4.3.3. Oscillator Register,CM_OSC
4.3.4. Control Register, CM_CTRL
4.3.5. Status Register, CM_STAT
4.3.6. Lock Register, CM_LOCK
4.3.7. Local Memory Bus CycleCounter, CM_LMBUSCNT
4.3.8. Auxiliary Oscillator Register, CM_AUXOSC
4.3.9. SDRAM Status and ControlRegister, CM_SDRAM
4.3.10. Core Module Voltage ConfigurationRegisters, CM_VOLTAGE_CTL0-3
4.3.11. Core Module InitializationRegister, CM_INIT
4.3.12. Reference Clock Cycle Counter Register,CM_REFCNT
4.3.13. Flag registers
4.3.14. Interrupt control registers
4.4. SDRAM SPD memory
5. Using Core Modules with an Integrator/AP
5.1. About the system architecture
5.1.1. Configuring little or big-endian operation
5.2. Module ID selection
5.2.1. Module address decoding
5.3. Top-level memory map
5.3.1. Global SDRAM access
5.3.2. Access arbitration
5.4. System bus bridge
5.4.1. Processor accesses to the system bus
5.4.2. Motherboard accesses to the SDRAM DIMM
5.4.3. System bus signal routing
5.5. Interrupt control
A. Signal Descriptions
A.2.1. HDRB socket pinout
A.2.2. HDRB plug pinout
A.2.3. Through-board signalconnections
A.2.4. HDRB signal descriptions
A.3. Trace connectors pinout
A.4. Logic analyzer connectors
A.4.1. Logic analyzer connectorHADDR
A.4.2. Logic analyzer connector CONTROL
A.4.3. Logic analyzer connector HDATA[31:0]
A.4.4. Logic analyzer connector HDATA[63:32]
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Timing specification
B.2.1. Integrator timing parameters and theAMBA Specification
B.2.2. AHB system bus timing parameters
B.2.3. Notes on FPGA timing analysis
B.3. Mechanical details

List of Figures

1.1. Integrator/CM10200E layout
1.2. ARM Integrator/CM10200E block diagram
1.3. Links and indicators
1.4. Test points
2.1. Power connector
2.2. Multi-ICE connection to a core module
2.3. Assembled Integrator system
3.1. ARM10200E reference device blockdiagram
3.2. Core module FPGA block diagram
3.3. FPGA configuration
3.4. Core module Reset and Power-ManagementController
3.5. Voltage control registers
3.6. Core voltage circuit
3.7. Location of the voltage control resistors
3.8. Core module clock generator
3.9. Internal test chip clock control
3.10. ARM PLLCLK divider control
3.11. AUXCLK divider control
3.12. JTAG connector, CFGEN link, and LED
3.13. JTAG data path
3.14. JTAG clock path
3.15. Multi-ICE connector pinout
3.16. Trace connection
4.1. Effect of remap
4.2. SDRAM repeat mapping for a 64MB DIMM
4.3. ID Register, CM_ID
4.4. Oscillator Register, CM_OSC
4.5. Control Register, CM_CTRL
4.6. Status Register, CM_STAT
4.7. Lock Register, CM_LOCK
4.8. Auxiliary Oscillator Register, CM_AUXOSC
4.9. SDRAM Status and Control Register,CM_SDRAM
4.10. Voltage control registers
4.11. Initialization Register, CM_INIT
4.12. Interrupt control
4.13. IRQ and FIQ bit assignments
5.1. FPGA functional diagram
5.2. Top-level memory map
5.3. Core module local and alias addressesfor SDRAM DIMM
5.4. Processor writes to the system bus
5.5. Processor reads from the system bus
5.6. System bus writes to SDRAM
5.7. System bus reads from SDRAM
5.8. Signal rotation on HDRB
5.9. Interrupt architecture (AP image)
A.1. HDRA plug pin numbering
A.2. HDRB socket pin numbering
A.3. HDRB plug pin numbering
A.4. AMP Mictor connector
B.1. Board outline

List of Tables

1.1. LED functional summary
1.2. Test point functions
3.1. Controllable processor configuration signals
3.2. Fixed value processor configuration signals
3.3. CFGSEL[1:0] encoding
3.4. Core and cache power enable
3.5. Wakeup events
3.6. Reset and power-management signal descriptions
3.7. Internal clock selection
3.8. Test clock output
3.9. Clock control signal assignment
3.10. Values for output divider
3.11. JTAG signal description
3.12. Link LK1 positions
4.1. Core module memory map
4.2. Private SDRAM memory map on power-up
4.3. Configured private SDRAM
4.4. Core module registers
4.5. ID Register, CM_ID bit assignment
4.6. Oscillator Register, CM_OSC bit assignment
4.7. Control Register, CM_CTRL register bit assignment
4.8. Status Register, CM_STAT register bit assignment
4.9. Lock Register, CM_LOCK bit assignment
4.10. Auxiliary Oscillator Register, CM_AUXOSC bit assignment
4.11. SDRAM Status and Control Register, CM_SDRAM bit assignment
4.12. Core Operating Voltage Register, CM_VOLTAGE_CTL0
4.13. Cache Operating Voltage Register, CM_VOLTAGE_CTL1
4.14. Core Power-Down Voltage Register, CM_VOLTAGE_CTL2
4.15. Cache Power-Down Voltage Register, CM_VOLTAGE_CTL3
4.16. Initialization Register, CM_INIT bit assignment
4.17. Flag registers
4.18. Interrupt control registers
4.19. IRQ and FIQ register bit assignment
4.20. IRQ register bit assignment
4.21. SPD memory contents
5.1. Core module address decode
5.2. Core module interrupts
A.1. Bus bit assignment
A.2. Signal cross-connections (example)
A.3. HDRB signal description (AHB)
A.4. Trace connector one pinout
A.5. Trace connector two pinout
A.6. Connector HADDR pinout
A.7. Connector CONTROL
A.8. Connector HDATA[31:0] pinout
A.9. HDATA[63:32] pinout
B.1. Core module electrical characteristics
B.2. Current requirements
B.3. Clock and reset parameters
B.4. AHB slave input parameters
B.5. AHB slave output parameters
B.6. Bus master input timing parameters
B.7. Bus master output timing parameters
B.8. AHB arbiter input parameters
B.9. AHB arbiter output parameters

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited, except as otherwise stated below in this proprietarynotice. Other brands and names mentioned herein may be the trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt frompart 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Integrator generates, uses, and can radiate radio frequencyenergy and may cause harmful interference to radio communications.However, there is no guarantee that interference will not occurin a particular installation. If this equipment causes harmful interferenceto radio or television reception, which can be determined by turningthe equipment off or on, you are encouraged to try to correct theinterference by one or more of the following measures:

  • ensure attached cables donot lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment andthe receiver

  • connect the equipment into an outlet on a circuitdifferent from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technicianfor help


It is recommended that wherever possible Shielded interfacecables be used.

Revision History
Revision A January2003 First release
Copyright © 2003 ARM Limited. All rights reserved. ARM DUI 0161A