| Copyright © 2002-2011 ARM. All rights reserved. | ARM DUI 0175N |
| Non-Confidential | ID052111 |
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| Home > RealView Debugger Commands > Alphabetical command reference > CACHELINE |
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Prints information about a specific cache line.
CACHELINE [,level:n] {,instruction | ,data} ,set:index[,way:index]
where:
,level:nThe cache level. If omitted, information about the
level 1 cache is displayed. This qualifier can be shortened to l.
,instructionDisplay a summary of the instruction cache.
,dataDisplay a summary of the data cache.
,set:indexDisplay details about the specific set line. This
qualifier can be shortened to s.
,way:indexDisplay details about a specific way line in the
specified set. This qualifier can be shortened to w.
If the processor has a unified cache, you can omit the i and d qualifiers.
If the processor has a Harvard cache, you must specify i or d.
Prints information about a specific cache line. If no way is specified, all cache lines in the same set are printed.
This command is supported on the following processors:
ARM1136
ARM1156
Cortex-A8.
To display all way lines for set line 10 in the level 1 instruction cache on an ARM1136JF-S, enter:
> cacheline,i,set:10
Instruction cache line in set 10; way 0 contains physical address range Phy<0x00004140>..Phy<0x0000415F>
Instruction cache line in set 10; way 1 contains physical address range Phy<0x00000140>..Phy<0x0000015F>
Instruction cache line in set 10; way 2 contains physical address range Phy<0x00003140>..Phy<0x0000315F>
Instruction cache line in set 10; way 3 contains physical address range Phy<0x00001140>..Phy<0x0000115F>
| Copyright © 2002-2011 ARM. All rights reserved. | ARM DUI 0175N |
| Non-Confidential | ID052111 |
| PDF version | |
| Home > RealView Debugger Commands > Alphabetical command reference > CACHELINE |