2.3.146. TRACEINSTRFETCH

Enables you to set a tracepoint on instruction fetch from memory.

Note

This command is valid only for ETM-based hardware targets.

Syntax

TRACEINSTRFETCH [,qualifier...] {address | address-range}

where:

qualifier

Is an ordered list of zero or more qualifiers. The possible qualifiers are described in List of qualifiers.

address

Specifies the address at which the tracepoint is placed.

address-range

Specifies the address range at which the tracepoint is placed.

Description

This command sets a tracepoint at the address or address range you specify that triggers when an instruction opcode is fetched from memory in the indicated address range.

Note

Use this type of tracepoint with care, because not all instructions that are fetched are executed, and because the fetch from memory occurs several cycles before execution and possibly not in execution order.

The tracepoint type is by default to trigger, that is, start collecting trace information into the trace buffer. You can modify the action using the hw_out: qualifier to, for example, stop tracing.

List of qualifiers

The command qualifiers are as follows, but not all qualifiers are available for all of the supported trace targets:

hw_ahigh:(n)

Specifies the high address for an address-range tracepoint. The low address is specified by the standard tracepoint address.

For example, to set a tracepoint that triggers for any address in the range 0x1000-0x1200, enter the command:

TRACEINSTRFETCH,hw_ahigh:0x1200 0x1000

This is equivalent to the command:

TRACEINSTRFETCH 0x1000..0x1200
hw_and:{id | "then-id"}

Perform an and or an and-then conjunction with an existing tracepoint. For example, hw_and:2, or hw_and:"then-2", where 2 is the tracepoint ID of another tracepoint.

The parentheses are optional.

In the and form, the conditions associated with both tracepoints are chained together, so that the action associated with the second tracepoint is performed only when both conditions match at the same time.

In the and-then form, when the condition for the first tracepoint is met, the second tracepoint is enabled. When the second tracepoint condition is matched, even if the first condition no longer matches, the actions associated are performed.

Note

You must include the quotes when using the and-then form.

Theid is one of:

  • the tracepoint list index of an existing of tracepoint

  • prev for the last tracepoint specified for this connection

  • next for the target of this condition.

hw_dhigh:(n)

Specifies the high data value for a data-range tracepoint. The low data value is specified by the hw_dvalue qualifier.

For example, to set a tracepoint that triggers when an instruction opcode in the range 0xEA000040-0xEA00004F is fetched from code in the range 0x1FA00-0x1FAFF, enter the command:

TRACEINSTRFETCH,hw_dvalue:0xEA000040,hw_dhigh:0xEA00004F 0x1FA00..0x1FAFF
hw_dmask:(n)

Specifies the data value mask for a data-range tracepoint. The data value to which the mask is applied is specified by the hw_dvalue qualifier. The data value range is determined by masking lower order bits out of the specified data value.

For example, to set a tracepoint that triggers when an instruction having a basic opcode 0xEA000040 but with any value in bits [15:8] is fetched from addresses in the range 0x1FA00-0x1FAFF, enter the command:

TRACEINSTRFETCH,hw_dvalue:0xEA000040,hw_dmask:0xFFFF00FF 0x1FA00..0x1FAFF
hw_dvalue:(n)

Specifies a data value to be compared to values transmitted on the processor data bus.

For example, to set a tracepoint that triggers when an instruction with an opcode of 0xEA000040 is fetched from an address in the range 0x1FA00-0x1FAFF, enter the command:

TRACEINSTRFETCH,hw_dvalue:0xEA000040 0x1FA00..0x1FAFF
hw_in:{s}

Input trigger tests. The string s is specific to the trace connection being used. For the ARM ETM, the following case-sensitive forms are defined:

Ignore Security Level=Yes|No

Enables Secure World and Normal World data comparisons for processors that implement the TrustZone technology:

Yes

Match when the processor is in any mode. This is the default.

No

Match only when the processor is in the mode specified by the address suffix:

  • S:address indicates Secure World.

  • N:address indicates Normal World.

For example, to capture trace when an instruction is fetched from the Secure World address 0x8000, enter the command:

TRACEINSTRFETCH,hw_in:{Ignore Security Level=No} S:0x8000.

Size of Data Access=s

This determines the following:

  • for data accesses, the size of the data transfer

  • for instruction accesses, the size of the instruction accessed.

The size s is one of:

Any

Depends on the implementation:

  • halfword for Thumb code

  • word for ARM code.

This is the default.

Halfword

16-bit accesses (Thumb code).

Word

32-bit accesses (ARM code).

hw_not:{s}

Use this qualifier to invert the sense of an address, data, or hw_and term specified in the same command. The argument s can be set to:

addr

Invert the tracepoint address value.

data

Invert the tracepoint value.

then

Invert an associated hw_and:{then} condition.

For example, to capture trace when a data value does not match a mask, enter the command:

TRACEINSTRFETCH,hw_not:data,hw_dmask:0x00FF ...

The trace commands require an address value, and the addr variant of hw_not uses this address. For example, to trace execution at addresses other than the range 0x10040 to 0x10060, that is, exclude this region from the trace, enter the command:

TRACEINSTRFETCH,hw_not:addr 0x10040..0x10060

The hw_not:then variant of the command is used in conjunction with hw_and to form or and nand-then conditions.

hw_out:{s}

Output trigger tests. The string s is specific to the trace connection being used. For the ARM ETM, the following case-sensitive forms are defined:

"Tracepoint Type=s"

Specify the trace action when an instruction is fetched from an address in the specified range, where s is:

Trigger

Output a trigger event to the TPA.

Start Tracing

Start trace capture.

Stop Tracing

Stop trace capture.

Trace Instr

Trace instructions only.

Trace Instr and Data

Trace instructions and data.

Note

An address range can be specified only for Trace Instr and Trace Instr and Data.

For example, to trace only instructions when an instruction is fetched from an address in the range 0x1E000-0x1FF00, enter the command:

TRACEINSTRFETCH,hw_out:"Tracepoint Type=Trace Instr" 0x1E00..0x1FF00
hw_passcount:(n)

Specifies the number of times that the specified condition has to occur to trigger the tracepoint. You can use this option to set up and use the ARM ETM counter hardware, if the ETM has counters and there is one available for use. ETM counters are 32 bits.

modify:(n)

Instead of creating a new tracepoint, modify the tracepoint with tracepoint ID number n by replacing the address expression and the qualifiers of the existing tracepoint to those specified in this command.

Note

You cannot use this qualifier with the hw_and qualifier to change a non-chained tracepoint to a chained tracepoint. However, you can modify a chained tracepoint with any other qualifier and also change the address expression.

Alias

TRCIFETCH is an alias of TRACEINSTRFETCH.

See also

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