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The items in this glossary are listed in alphabetical order, with any symbols and numerics appearing at the end.
A debug target connection item that can connect to one or more target processors. The term is normally used when describing the RealView Debugger Connection Control window.
See ARM Developer Suite.
Angel is a software debug monitor that runs on the target and enables you to debug applications running on ARM-based hardware. Angel is commonly used where a JTAG emulator, such as Multi-ICE, is not available.
A suite of software development applications, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of RISC processors. ADS is superseded by RealView Developer Suite (RVDS).
See Also RealView Developer Suite.
A word that encodes an operation for an ARM processor operating in ARM state. ARM instructions must be word-aligned.
A processor that is executing ARM instructions is
operating in ARM state. The processor switches to Thumb state (and
to recognizing Thumb instructions) when directed to do so by a state-changing
instruction such as BX, BLX.
See Also Thumb state.
Asynchronous execution of a command means that the debugger accepts new commands as soon as this command has been started, enabling you to continue do other work with the debugger.
See Call Stack.
Memory organization where the least significant byte of a word is at the highest address and the most significant byte is at the lowest address in the word.
See Also Little-endian.
RealView Debugger uses the term board to refer to a target processor, memory, peripherals, and debugger connection method.
The board file is the top-level
configuration file, normally called rvdebug.brd,
that references one or more other files.
A user defined point at which execution stops in order that a debugger can examine the state of memory and registers.
See Also Conditional breakpoint, Default breakpoint, Hardware breakpoint, Software breakpoint, and Unconditional breakpoint.
This is a list of procedure or function call instances on the current program stack. It might also include information about call parameters and local variables for each instance.
A breakpoint that halts execution when a particular condition becomes True. The condition normally references the values of program variables that are in scope at the breakpoint location.
See Also Breakpoint, Default breakpoint, Hardware breakpoint, Software breakpoint, and Unconditional breakpoint.
See Pop-up menu.
In the context of Integrator, an add-on development board that contains an ARM processor and local memory. Core modules can run stand-alone, or can be stacked onto Integrator motherboards.
See Also Integrator.
See Program Status Register.
See Debug Communications Channel.
A debug communications channel enables data to be passed between RealView Debugger and the EmbeddedICE logic on the target using the JTAG interface, without stopping the program flow or entering debug state.
ARM code generation tools generate debug information in DWARF2 format by default. From RVCT v2.2, you can optionally generate DWARF3 format (Draft Standard 9).
A breakpoint that does not have a condition qualifier or an action assigned. A default breakpoint is always an unconditional breakpoint.
See Also Breakpoint, Conditional breakpoint, Hardware breakpoint, Software breakpoint, and Unconditional breakpoint.
A deprecated option or feature is one that you are strongly discouraged from using. Deprecated options and features are to be removed in future versions of the product.
DSPs are special processors designed to execute repetitive, maths-intensive algorithms. Embedded applications might use both ARM processor cores and DSPs.
A 64-bit unit of information.
See Digital Signal Processor.
See Debug With Arbitrary Record Format.
Executable and Linking Format. ARM code generation tools produce objects and executable images in ELF format.
A block of logic, embedded in the hardware, that is connected to the address, data, and status signals of the processor. It broadcasts branch addresses, and data and status information in a compressed protocol through the trace port. It contains the resources used to trigger and filter the trace output.
The EmbeddedICE logic is an on-chip logic block that provides TAP-based debug support for ARM processor cores. It is accessed through the TAP controller on the ARM core using the JTAG interface.
See Also IEEE1149.1.
In the context of target connection hardware, an emulator provides an interface to the pins of a real core (emulating the pins to the external world) and enables you to control or manipulate signals on those pins.
A debug target processor, normally accessed through an access-provider connection.
See Embedded Trace Macrocell.
See Extended Target Visibility.
Extended Target Visibility enables RealView Debugger to access features of the underlying target, such as chip-level details provided by the hardware manufacturer or SoC designer.
Software that emulates the action of a hardware unit dedicated to performing arithmetic operations on floating-point values.
See Floating Point Emulator.
A 16-bit unit of information.
A breakpoint that is implemented using non-intrusive additional hardware. Hardware breakpoints are the only method of halting execution when the location is in Read Only Memory (ROM). Using a hardware breakpoint often results in the processor halting completely. This is usually undesirable for a real-time system.
See Also Breakpoint, Conditional breakpoint, Default breakpoint, Software breakpoint, and Unconditional breakpoint.
The IEEE Standard that defines TAP. Commonly (but incorrectly) referred to as JTAG.
See Also Test Access Port.
A range of ARM hardware development platforms. Core modules are available that contain the processor and local memory.
An IEEE group focussed on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors. For more information see IEEE Standard, Test Access Port and Boundary-Scan Architecture specification 1149.1 (JTAG).
See Joint Test Action Group.
A protocol converter that converts low-level commands from RealView Debugger into JTAG signals to the processor, for example to the EmbeddedICE logic and to the ETM.
Memory organization where the least significant byte of a word is at the lowest address and the most significant byte is at the highest address of the word.
See Also Big-endian.
The ARM JTAG emulator debug tool for embedded systems. ARM registered trademark.
Also known as Context menu. A menu that is displayed temporarily, offering items relevant to your current situation. Obtainable in most RealView Debugger windows or panes by right-clicking with the mouse pointer inside the window. In some windows the pop-up menu can vary according to the line the mouse pointer is on and the tabbed page that is currently selected.
The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit and the register bank. It excludes optional coprocessors, caches, and the memory management unit.
Accumulation of statistics during execution of a program being debugged, to measure performance or to determine critical areas of code.
Contains information about the current execution context. It is also referred to as the Current PSR (CPSR), to emphasize the distinction between it and the Saved PSR (SPSR), which records information about an alternate processor mode.
See Program Status Register.
See Remote Debug Interface.
A small program that, when integrated into your target application or Real-Time Operating System (RTOS), enables you to observe and debug your target while parts of your application continue to run.
The most recent version of the ARM simulator, RealView ARMulator ISS is supplied with RealView Developer Suite. It communicates with a debug target using RV-msg, through the RealView Connection Broker interface, and RDI.
See Also RDI and RealView Connection Broker.
RealView Compilation Tools is a suite of tools, together with supporting documentation and examples, that enables you to write and build applications for the ARM family of RISC processors.
RealView Connection Broker is an execution vehicle that enables you to connect to simulator targets on your local system, or on a remote system. It also enables you to make multiple connections to the simulator.
See Also RealView ARMulator ISS.
Part of the RealView Debugger product that extends the debugging capability with the addition of real-time program and data tracing. It is available from the Code window.
A JTAG-based debug solution to debug software running on ARM processors.
The Remote Debug Interface (RDI) is an ARM standard procedural interface between a debugger and the debug agent. RDI gives the debugger a uniform way to communicate with:
a simulator running on the host (for example, RVISS)
a debug monitor running on hardware that is based on an ARM core accessed through a communication link (for example, Angel)
a debug agent controlling an ARM processor through hardware debug support (for example, RealView ICE or Multi-ICE).
Remote_A is a software protocol converter and configuration interface. It converts between the RDI 1.5 software interface of a debugger and the Angel Debug Protocol used by Angel targets. It can communicate over a serial or Ethernet interface.
Real Time Operating System.
See RealView Compilation Tools.
See RealView ARMulator ISS.
A scan chain is made up of serially-connected devices that implement boundary-scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain. Processors might contain several shift registers to enable you to access selected parts of the device.
The range within which it is valid to access such items as a variable or a function.
A file specifying a sequence of debugger commands
that you can submit to the command-line interface using the include command.
A mechanism whereby I/O requests made in the application code are communicated to the host system, rather than being executed on the target.
A simulator executes non-native instructions in software (simulating a core).
A breakpoint that is implemented by replacing an instruction in memory with one that causes the processor to take exceptional action. Because instruction memory must be altered software breakpoints cannot be used where instructions are stored in read-only memory. Using software breakpoints can enable interrupt processing to continue during the breakpoint, making them more suitable for use in real-time systems.
See Also Breakpoint, Conditional breakpoint, Default breakpoint, Hardware breakpoint, and Unconditional breakpoint.
An instruction that causes the processor to call a programmer-specified subroutine. Used by the ARM standard C library to handle semihosting.
Saved Program Status Register.
See Also Program Status Register.
See Software Interrupt.
Synchronous execution of a command means that the debugger stops accepting new commands until this command is complete.
Setting several processors to a particular program location and state, and starting them together.
Stopping several processors in such a way that they stop executing at the same instant.
See Test Access Port.
Logic on a device which enables access to some or all of that device for test purposes. The circuit functionality is defined in Std. IEEE1149.1.
See Also Test Access Port and IEEE Std. 1149.1.
The target board, including processor, memory, and peripherals, real or simulated, on which the target application is running.
Target vehicles provide RealView Debugger with a standard interface to disparate targets so that the debugger can connect easily to new target types without having to make changes to the debugger core software.
Essentially the debugger itself, this contains the
basic debugging functionality. TVS contains the run control, base
multitasking support, much of the command handling, and target knowledge,
such as memory mapping, lists, rule processing, board file and .bcd files,
and data structures to track the target environment.
The port used to access the TAP Controller for a given device. Comprises TCK, TMS, TDI, TDO, and nTRST (optional).
One halfword or two halfwords that encode an operation for an ARM processor operating in Thumb state. Thumb instructions must be halfword-aligned.
A processor that is executing Thumb instructions
is operating in Thumb state. The processor switches to ARM state
(and to recognizing ARM instructions) when directed to do so by
a state-changing instruction such as BX, BLX.
See Also ARM state.
A tracepoint can be a line of source code, a line of assembly code, or a memory address. In RealView Debugger, you can set a variety of tracepoints to determine exactly what program information is traced.
In the context of breakpoints, a trigger is the action of noticing that the breakpoint has been reached by the target and that any associated conditions are met.
In the context of tracing, a trigger is an event that instructs the debugger to stop collecting trace and display the trace information around the trigger position, without halting the processor. The exact information that is displayed depends on the position of the trigger within the buffer.
See Target Vehicle Server.
A breakpoint that does not have a conditional qualifier assigned, and so always halts execution.
See Also Breakpoint, Conditional breakpoint, Default breakpoint, Hardware breakpoint, and Software breakpoint.
A standard for floating-point coprocessors where several data values can be processed by a single instruction.
See Vector Floating Point.
A watch is a variable or expression that you require the debugger to display at every step or breakpoint so that you can see how its value changes. The Watch pane is part of the RealView Debugger Code window that displays the watches you have defined.
In RealView Debugger, this is a hardware breakpoint.
A 32-bit unit of information.
| Copyright © 2002-2005 ARM Limited. All rights reserved. | ARM DUI 0182G |
| Non-Confidential | |
| PDF version | |
| Home > Glossary |