RVISS is the ARM processor simulator supplied with RealView Developer Suite (RVDS). This section describes how to configure the RDI interface to RVISS.
Note
The RDI connection to RVISS in RealView Debugger is deprecated in this release.
RVISS also provides a RealView Connection Broker interface. See Working with Simulator Broker connections for details on configuring this interface.
For the ARMulator RDI target entry, the
configuration dialog box is shown in Figure 5.9.
The ARMulator Configuration dialog box (Figure 5.9) enables you to examine and change the following settings:
- Processor
Use the drop-down list to specify which ARM processor you want RVISS to simulate, for example,
ARM920TorARM966E-S.- Clock
Choose between simulating a processor clock running at a speed that you can specify, or executing instructions in real-time by setting this value to
0. You can use units ofHz,KHz,MHzandGHz, for example50MHz.Changing this value does not affect the real time taken to run a program. Instead, it affects the values that the semihosting
time()functions return to the program.- Options
Enable this to include a simulation of the Floating Point Accelerator (FPA) coprocessor included in the ARM7500FE processor.
- Debug Endian
Select the byte order of the modeled system. This setting:
sets RealView Debugger to work with the appropriate byte order
sets the byte order of models that do not have a CP15 coprocessor
sets the byte order of models that do have a CP15 coprocessor if the Start target Endian option is set to Debug Endian.
- Start target Endian
Select the way in which the byte order of RVISS models that have a CP15 coprocessor is determined:
Select the Debug Endian radio button to instruct the model to use the byte order set in the Debug Endian group.
Select the Hardware Endian radio button to instruct the model to simulate the behavior of real hardware.
The possible combinations of Debug Endian and Start target Endian are shown in Table 5.1.
Table 5.1. RealView ARMulator ISS Endian settings
Usage Debug Endian Start target Endian A target that is always little-endian. This is the default. Little Debug Endian A target that is always big-endian Big Debug Endian A big-endian target where the code and the processor core start in little-endian mode, and switch to big-endian in the initialization code Big Hardware Endian - Memory Map File
Specify a memory map file for use with RVISS. When you connect, the map details are listed with the other connection-related messages.
A map file that is specified in this way is not shown in Map tab of the Process Control pane. Therefore, you must edit the map file directly to make changes to the memory map, then disconnect and reconnect. Alternatively, you can use the
Memory_blockconfiguration item to specify a memory map to RealView Debugger. See Configuring a memory map for an example explaining how to do this.Note
Be aware that the
MAPFILETOLOADsetting in the RVISSperipherals.amifile overrides the map file you specify in this dialog box.- Floating Point Coprocessor
Use the drop-down list to specify the Vector Floating Point (
VFP) coprocessor included with some ARM CPUs. The default isNo_FPU.- MMU/PU Initialization
If you are simulating a processor with an active Memory Management Unit (MMU), specify
DEFAULT_PAGETABLES, otherwise selectNO_PAGETABLES. See ARM Architecture Reference Manual for more information.
See RealView ARMulator ISS User Guide for more information on how these settings apply to RVISS.
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