RealView ® Debugger TargetConfiguration Guide

Version 3.1

Table of Contents

About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback on RealView Debugger
Feedback on this book
1. Introduction
1.1. About connection configuration
1.1.1. What is connection configuration?
1.1.2. Connect to Target window
1.1.3. Connection Propertieswindow
1.2. Default configuration files
1.2.1. Debug Configurationboard file
1.2.2. Debug Configuration settings
1.2.3. RealView configuration files
1.2.4. RVISS configuration files
1.2.5. ISSM configuration files
1.2.6. SoC Designer configuration files
1.2.7. RTSM configuration files
1.2.8. Board/Chip Definition files
1.3. How configuration files are linkedtogether
1.3.1. See also
1.4. What the configuration files contain
1.4.1. See also
1.5. Locating the configuration files
1.5.1. The install directory
1.5.2. The RealView Debugger home directory
1.5.3. The RealView Debugger search path
1.5.4. Saving and restoring connection properties
1.6. Summary of supplied BCD files
1.6.1. See also
2. Customizing a Debug Interface configuration
2.1. About customizing a Debug Interfaceconfiguration
2.1.1. See also
2.2. Customizing a RealView ICE Debug Interfaceconfiguration
2.2.1. Procedure for non-CoreSight developmentplatforms containing ARM processors only
2.2.2. Procedure for development platformscontaining CoreSight components
2.2.3. Procedure for development platformscontaining non-ARM processors
2.2.4. Considerations when customizing RealView ICE DebugInterface configurations
2.3. Customizing an RVISS Debug Interfaceconfiguration
2.3.1. Procedure for customizing an RVISSDebug Interface configuration
2.3.2. Considerations when customizing RVISS Debug Interfaceconfigurations
2.4. Customizing an ISSM Debug Interfaceconfiguration
2.4.1. Procedure for customizing an ISSMDebug Interface configuration
2.5. Customizing a SoC Designer Debug Interfaceconfiguration
2.5.1. Customizing a SoC Designer Debug Interfaceconfiguration (SoC Designer not running)
2.5.2. Customizing a SoC Designer Debug Interfaceconfiguration (SoC Designer running)
2.6. Customizing an ISSM Debug Interfaceconfiguration for RTSM
2.6.1. Procedure
3. Customizing a Debug Configuration
3.1. About customizing a Debug Configuration
3.1.1. Relationship between connection propertiesand Debug Configurations
3.1.2. Managing configuration settings
3.1.3. Using the examples
3.2. Viewing the connection properties
3.2.1. Displaying the Connection Propertieswindow
3.2.2. Identifying groups in the List ofEntries pane
3.2.3. Identifying settings in the SettingsValues pane
3.2.4. Debug Configuration entries
3.2.5. The Debug Configuration Advanced_Informationblock
3.3. Changing connection settings
3.3.1. Changing entries containing user-informationvalues
3.3.2. Changing a specific value back tothe default value
3.3.3. Changing the order of settings thathave multiple values
3.3.4. Removing instances from multi-valuesettings
3.3.5. Avoiding conflicts between linkedboard groups
3.4. Loading a different board file
3.4.1. Manually loading a board file
3.4.2. Forcing the load ofa specific board file on startup (global configuration)
3.4.3. Forcing the load of a specific boardfile on startup (workspace configuration)
3.5. Disabling a Debug Configuration
3.5.1. Procedure
3.6. Specifying connect and disconnectmode
3.6.1. Configuring connect mode
3.6.2. Configuring disconnect mode
3.7. Creating a target-specific Advanced_Informationgroup
3.7.1. Before you start
3.7.2. Procedure
3.8. Configuring vector catch
3.8.1. Default settings for processor exceptions
3.8.2. Setting vector catch for all targets
3.8.3. Setting vector catch for individualtargets
3.8.4. Temporarily overriding the vector catch for an existingconnection
3.8.5. Considerations when setting SVC vector catch (hardwaretargets)
3.9. Configuring Semihosting
3.9.1. Configuring semihosting for all targets
3.9.2. Configuring semihosting for individual targets
3.9.3. Considerations when configuring semihosting
3.10. Configuring the CLI commands for hardwarecross-triggering
3.10.1. Procedure
3.11. Configuring a connection sequencefor multiple targets
3.11.1. Setting a generic connection sequencefor a Debug Configuration
3.11.2. Specifying a target-specific connectionsequence
3.12. Running CLI commands automaticallyon connection
3.12.1. Before you start
3.12.2. Procedure
3.13. Configuring RealMonitor for connectionsthrough RealView ICE
3.13.1. Restrictions on using RealMonitorwith RealView ICE
3.13.2. Rules for connecting RealView ICEto a running target
3.13.3. Basic procedure
3.13.4. Customizing the Debug Configurationused for enabling RealMonitor
3.13.5. Customizing the DebugConfiguration used for debugging with RealMonitor
3.13.6. Loading an image before using RealMonitor
3.13.7. Working with RealMonitor
3.14. Flash programming
3.14.1. See also
3.15. Using the Thumb-2EE helper macro
3.15.1. Loading the Thumb-2EE helper macrofor a single processor system
3.15.2. Loading the Thumb-2EE helper macrofor a multiprocessor system
3.15.3. Using the Thumb-2EEhelper macro with breakpoints and tracepoints
3.15.4. Examining the definition of the handleraddr()macro
3.16. Restoring your .brd file
3.16.1. Procedure
3.17. Example of setting up an Integratorboard and core module
3.17.1. Procedure Summary
3.17.2. Setting up the hardware and DebugInterface
3.17.3. Creating the new Debug Configuration
3.17.4. Configuring the new Debug Configuration
3.17.5. Linking board groups to the new DebugConfiguration
3.17.6. Connecting to the new target
3.17.7. Viewing the new target definition
3.18. Troubleshooting Debug Configurations
3.18.1. Problems with target-specific settings
3.18.2. Problems with missing or corrupt configurationfiles
3.18.3. Status of a Debug Configuration reportsGeneral Error
4. Configuring Custom Memory Maps, Registers and Peripherals
4.1. About configuring custom memory maps,registers, and peripherals
4.1.1. BCD file configuration entries
4.1.2. The BCD file Advanced_Informationblock
4.1.3. Board, chip, and component groups
4.1.4. Suggested naming convention for memorymap related settings groups
4.1.5. Using the examples
4.2. Linking a board, chip, or componentgroup to a Debug Configuration
4.2.1. Linking one board groupto a Debug Configuration
4.2.2. Linking several board groups to aDebug Configuration
4.2.3. Linking one or more board groups toanother board group
4.2.4. Linking one or more board groups toa multiprocessor Debug Configuration
4.3. Using the supplied BCD files
4.3.1. See also
4.4. Creating a BCD file to use as a template
4.4.1. Procedure
4.5. Basic procedure for creating BCD files
4.5.1. Managing configuration settings
4.5.2. See also
4.6. Creating a new BCD file
4.6.1. Procedure
4.7. Creating and naming a board, chip,or component group
4.7.1. Adding a new BCD group
4.7.2. Renaming a BCD group
4.8. Linking BCD groups
4.8.1. Linking a BCD group to a Debug Configuration
4.8.2. Linking a BCD group to another BCDgroup
4.8.3. Linking multiple BCD groups to a DebugConfiguration
4.9. Setting top of memory
4.9.1. About top of memory, stack and heap
4.9.2. Examining the top of memory value
4.9.3. Setting top of memory
4.10. Creating a memory map block
4.10.1. Preparing the configuration
4.10.2. Procedure for creating a memory mapblock
4.10.3. Creating a memory map block that relatesto custom registers and peripherals
4.10.4. Viewing the memory map block
4.11. Creating an enumeration for settingregister values
4.11.1. Procedure
4.12. Creating a custom memory mapped register
4.12.1. Before you start
4.12.2. Creating the custom register
4.12.3. Defining a separate bit field fora custom register
4.13. Creating a custom peripheral
4.13.1. Before you start
4.13.2. Creating the custom peripheral
4.13.3. Creating the registers for a customperipheral
4.13.4. Defining separate bit fields for acustom peripheral register
4.14. Creating the register tab for displayingcustom registers and peripherals
4.14.1. Procedure
4.14.2. Viewing the customregisters and peripherals
4.15. Creating memory map rules
4.15.1. Before you start
4.15.2. Procedure
4.16. Setting up controlledmemory blocks
4.16.1. Before you start
4.16.2. Defining the controlled memory mapblocks
4.16.3. Defining the memory rules
4.16.4. Displaying the controlled memory mapblocks
4.17. Creating a concatenated register
4.17.1. Before you start
4.17.2. Procedure
4.17.3. Viewing the concatenated register
4.18. Troubleshooting BCD files
4.18.1. Expected memory map is not displayed
4.18.2. Duplicate definition warning messageson connecting
4.18.3. Overlapping un-controlled memory regionwarning messages on connecting
4.18.4. Map-Rule and Undefinedregister warnings
5. Debug Configuration Tutorial
5.1. About the Debug Configuration tutorial
5.1.1. About the development platform used in this tutorial
5.1.2. See also
5.2. Before starting the tutorial
5.2.1. See also
5.3. Creating a new Debug Configuration
5.3.1. See also
5.4. Configuring the new Debug Configuration
5.5. Creating the EtherRouter.bcd file
5.5.1. See also
5.6. Creating the AMDLANCE.bcd file
5.7. Creating the EtherRouter BOARD group
5.8. Creating the AMDLANCE CHIP group
5.9. Linking BCD groups
5.9.1. Linking the EtherRouter group to aDebug Configuration
5.9.2. Linking the AMDLANCE and KS32C50100chips to the EtherRouter board
5.9.3. See also
5.10. Creating the memory map
5.10.1. Creating the M_IO_REGS memory mapblock
5.10.2. Creating the M_I2C memory map block
5.10.3. Viewing the memory map
5.11. Creating the enumerations for theregister values
5.12. Creating a custom register
5.12.1. Creating the custom register
5.12.2. Defining the bit fields for the customregister
5.13. Creating the register tab for displayingcustom registers
5.13.1. Procedure
5.13.2. Viewing the custom registers
5.14. Setting up controlledmemory map blocks
5.15. Creating memory map rules
5.16. Displaying the controlled memory mapblocks
5.17. Creating a concatenated register
5.17.1. Procedure
5.17.2. Viewing the concatenated register
6. Programming Flash with RealView Debugger
6.1. Introduction to Flash programmingwith RealView Debugger
6.1.1. Summary of files used to program Flashon supported ARM development platforms
6.1.2. Summary of files used to program supportedFlash types on custom platforms
6.1.3. Summary of files usedto program custom Flash types on custom platforms
6.2. RealView Debugger files used for Flash programming
6.2.1. Evaluator-7T example
6.2.2. Flash-level code
6.2.3. Board-level code
6.2.4. ASCII MEthod file
6.2.5. Flash MEthod file
6.2.6. Board Chip Definition file
6.3. Using the pakflash utility
6.3.1. Command syntax
6.4. Programming Flash on the ARM developmentboards
6.4.1. About the ARM Integrator/AP board
6.4.2. Assigning a BCD file to a Debug Configuration
6.4.3. Reviewing the information containedin the Integrator/AP BCD file
6.4.4. Displaying the memory map in the ProcessControl pane
6.4.5. Programming an imageinto Flash on the Integrator/AP
6.5. Programming Flash for a custom developmentplatform
6.5.1. Third-party support for ARM core-baseddevelopment platforms
6.5.2. Programming a Flash type supportedby RealView Debugger
6.5.3. Programming a custom Flash type
6.6. Gathering information about your developmentplatform
6.6.1. Evaluator-7T example
6.7. Creating algorithmsfor a Flash type supported by RealView Debugger
6.7.1. The b_flashwrapper.s template file
6.7.2. Editing b_flashwrapper.s
6.7.3. Settings for the Evaluator-7T
6.8. Creating algorithms for a Flash typenot provided with RealView Debugger
6.8.1. Basic Procedure
6.8.2. C source file containingthe Flash-specific C functions
6.8.3. C header file
6.8.4. Assembly wrapper
6.9. Creating the Flash-level and board-levelAME files
6.9.1. Flash-level AME file format
6.9.2. Board-level AME fileformat
6.10. Generating the FME file
6.10.1. Locating the source and AME filesrequired
6.10.2. Specifying the compiler options
6.10.3. Specifying the assembler options
6.10.4. Specifying the linker options
6.10.5. Running the pakflashutility
6.10.6. See also
6.11. Checking the FME file with the dispflashutility
6.11.1. Evaluator-7T example
6.12. Creating a BCD file
6.12.1. Basic procedure for the Evaluator-7T example
6.12.2. Saving a copy of the template BCDfile
6.12.3. Creating the BOARD group in the BCDfile
6.12.4. Describing the memory map
6.12.5. Assigning your BCD file to a DebugConfiguration
6.12.6. Viewing the memory map
6.13. Programming an image into Flash
6.13.1. Writing the image to Flash
6.13.2. Using CLI commands to program Flash
6.13.3. Checking the contents of Flash
6.14. Troubleshooting
6.14.1. See also
A. Connection Properties Reference
A.1. About connection properties reference
A.1.1. The CONNECTION group
A.1.2. The DEVICE group
A.1.3. The BOARD, CHIP, and COMPONENT groups
A.1.4. Relationship between connections,boards, and chips
A.2. Debug Configuration generic groupsand settings
A.2.1. Connect_with
A.2.2. Remote
A.2.3. Advanced_Information block (base group)
A.2.4. Configuration
A.2.5. Auto_connect
A.2.6. Pre_connect
A.2.7. Description
A.2.8. Project
A.2.9. Disabled
A.2.10. Shared
A.2.11. BoardChip_name
A.2.12. Family_select
A.3. Debug Configuration Advanced_Informationsettings reference
A.3.1. Application_Load
A.3.2. ARM_config settings for a Debug Configuration
A.3.3. Logic_Analyzer
A.3.4. Cross_trigger
A.3.5. RTOS_config
A.3.6. Monitor
A.3.7. Pre_connect
A.3.8. Commands
A.3.9. Connect_mode
A.3.10. Disconnect_mode
A.3.11. Id_chip
A.3.12. Id_match
A.3.13. Chip_name
A.3.14. Endianess
A.3.15. Sw_bkpts
A.3.16. See also
A.4. Memory mapping Advanced_Informationsettings reference
A.4.1. ARM_config settings related to memorymapping
A.4.2. Memory_block
A.4.3. Map_rule
A.4.4. Register_enum
A.4.5. Register
A.4.6. Concat_Register
A.4.7. Peripherals
A.4.8. Register_Window
A.4.9. See also
B. ISSM Model Configuration Reference
B.1. Cortex-A8 model configuration
B.1.1. Summary of supported features forthe Cortex-A8 model
B.1.2. Limitations of the Cortex-A8 model
B.1.3. Cortex-A8 configurationparameters
B.1.4. Cortex-A8 memory map
B.1.5. Cortex-A8 peripheralregister mapping
B.2. Cortex-M1 Model configuration
B.2.1. Summary of supported features forthe Cortex-M1 model
B.2.2. Limitations of the Cortex-M1 model
B.2.3. Cortex-M1 configuration parameters
B.2.4. Cortex-M1 memory map
B.2.5. Cortex-M1 peripheralregister mapping
B.3. Cortex-M3 model configuration
B.3.1. Summary of supported features forthe Cortex-M3 model
B.3.2. Limitations of the Cortex-M3 model
B.3.3. Cycle and instruction counting feature
B.3.4. Cortex-M3 configuration parameters
B.3.5. Cortex-M3 memory map
B.3.6. Cortex-M3 peripheralregister mapping
B.4. Cortex-R4 model configuration
B.4.1. Summary of supported features forthe Cortex-R4 model
B.4.2. Limitations of the Cortex-R4 model
B.4.3. Cortex-R4 configuration parameters
B.4.4. Cortex-R4 memory map
B.4.5. Cortex-R4 peripheralregister mapping

List of Figures

1.1. Relationships in the Connect to Targetwindow
1.2. Example Connect to Target window
1.3. Example Connection Properties window
1.4. Relationship between configurationfiles
2.1. RealView ICE Debug Interface in theConnect to Target window
2.2. ARMulator configuration dialog box
2.3. Model Configuration Utility dialogbox
2.4. Model Configuration Utility dialogbox
3.1. Relationship between Connection Propertiesand the Connect to Target window
3.2. Connection Properties window
3.3. RealMonitor Debug Configuration fordebugging
3.4. RealMonitor Debug Configuration forrunning target
3.5. Debug Configuration settings
3.6. New Debug Configuration added
3.7. Displaying the new MP3Player connectionproperties
3.8. Board groups linked to the new connection
3.9. Connecting to the new target
3.10. AP tab in the Registers pane
4.1. Viewing .bcd files in the ConnectionProperties window
4.2. Linking one board to a connection
4.3. Linking two boards to a Debug Configuration
4.4. Board and chip groups for the Evaluator-7T
4.5. Tree view of the linked groups inthe Eval7T.bcd file
4.6. Board and chip groups for the EtherRouterboard
4.7. Tree view of the linked groups forthe EtherRouter board
4.8. Customizing a two-processor DebugConfiguration
4.9. Referencing two .bcd files in theConnection Properties window
4.10. Connection Properties window
4.11. Saving an existing BCD file witha new name
4.12. Viewing the new group in the BCDfile
4.13. Connection properties for a RealView-ICEDebug Configuration
4.14. Linking the CP BCD group
4.15. Assigning the KS32C50100 group
4.16. Linking a second board
4.17. Relating top_of_memory to singlesection program layout
4.18. Connection Properties for the RealView-ICEDebug Configuration
4.19. CM940T BOARD group selected
4.20. Viewing the contents of the new group
4.21. Configuring M_REGS
4.22. New memory map block in the ProcessControl pane
4.23. Memory map with image loaded
4.24. Creating enumerations
4.25. Creating bit field for registers
4.26. Creating bit fields for peripheralregisters
4.27. Register_Window group
4.28. The MP3_REGS group
4.29. MP3_REGS tab in the Registers pane
4.30. Settings for the R_FastRAM map rule
4.31. Settings for the R_SlowROM map rule
4.32. Settings for the R_FastRAM map rule
4.33. Settings for the R_SlowROM map rule
4.34. MP3_REGS tab in the Registers pane
4.35. New memory block in the Memory Maptab
4.36. Activated ROM memory block in theMemory Map tab
4.37. Concat_reg tab in Registers pane
4.38. User view showing concatenated register
4.39. User view showing concatenated registervalues
4.40. Memory map defined in the CM926EJ-S.bcdfile
4.41. Combined memory map for CM926EJ-S.bcdand CP.bcd
5.1. Linked groups for the EtherRouterboard
5.2. Tree view of the linked groups
5.3. RVISS_3 Debug Configuration in theConnect to Target window
5.4. Connection Properties for the EtherRouterDebug Configuration
5.5. Saving an existing BCD file witha new name
5.6. Connection properties for the RVIDebug Configuration
5.7. Linking the EtherRouter BCD group
5.8. Setting up the EtherRouter.bcd
5.9. Configuring the M_IO_REGS customregister
5.10. Configuring the M_I2C custom register
5.11. New memory map in the Process Controlpane
5.12. Memory map with Dhrystone image loaded
5.13. Creating enumerations
5.14. Creating bit field for a custom register
5.15. The EtherRouter Register_window group
5.16. EtherRouter tab in the Registerspane
5.17. M_FastRAM memory block
5.18. M_SlowROM memory block
5.19. Settings for the R_Fast_RAM map rule
5.20. Settings for the R_SlowROM map rule
5.21. EtherRouter tab in the Registerspane
5.22. RAM memory block in the Memory Maptab
5.23. Activated ROM memory block in theMemory Map tab
5.24. Core tab shown in the Registers pane
5.25. Concatenated register in EtherRoutertab
5.26. User view showing the concatenatedregisters
5.27. User view showing concatenated registervalues
6.1. New memory map in the Process Controlpane
6.2. The Flash Memory Control dialog box
6.3. Flash programming complete
6.4. Flash image details in memory map
6.5. Viewing the new memory map
A.1. How connections, boards, and chipsfit together
A.2. Viewing generic settings for aDebug Configuration
B.1. Cortex-A8 memory map
B.2. Cortex-M1 memory map
B.3. Cortex-M3 memory map
B.4. Cortex-R4 memory map

List of Tables

1.1. Default values for common connection attributes
2.1. RealView ICE Device names for CoreSight Components
2.2. Recommended settings for an ARM Integrator development board
2.3. RealView ARMulator ISS Endian settings 
3.1. Action performed after reset
3.2. Default settings for Processor Exceptions
3.3. CLI commands to enable and disable the ARM966E-S In and Outtriggers
3.4. Bit fields use for cross-triggering on ARM966E-S
3.5. Connection sequence using the generic Pre_connect setting
3.6. Pre_connect settings in Advanced_Information block
3.7. Connection sequence using target-specific Pre_connect setting
3.8. RealView ICE settings for RealMonitor
4.1. Suggested naming convention
4.2. Additional bitfields
4.3. C_R8_R9_concat settings
5.1. R8_R9_concat settings
6.1. Files used to program Flash on supported ARM developmentplatforms
6.2. Files used to program Flash types already supported
6.3. Evaluator-7T memory map
6.4. Evaluator-7T example settings
6.5. Memory map attributes
B.1. Cortex-A8 model configuration parameters
B.2. Cortex-A8 peripheral register mapping
B.3. Cortex-A8 PIC registers
B.4. Cortex-A8 RTC registers
B.5. Cortex-A8 Timer registers
B.6. Cortex-A8 UART registers
B.7. Cortex-A8 interrupts
B.8. Cortex-M1 model configuration parameters
B.9. Cortex-M1 peripheral register mapping
B.10. Cortex-M1 Timer registers
B.11. Cortex-M1 UART registers
B.12. Cortex-M1 interrupts
B.13. Cortex-M3 cycle count registers and symbols
B.14. Cortex-M3 model configuration parameters
B.15. Cortex-M3 peripheral register mapping
B.16. Cortex-M3 Timer registers
B.17. Cortex-M3 UART registers
B.18. Cortex-M3 interrupts
B.19. Cortex-R4 model configuration parameters
B.20. Cortex-R4 peripheral register mapping
B.21. Cortex-R4 PIC registers
B.22. Cortex-R4 Timer registers
B.23. Cortex-R4 RTC registers
B.24. Cortex-R4 UART registers
B.25. Cortex-R4 interrupts

Proprietary Notice

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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Where the term ARM is used it means “ARM or any of its subsidiariesas appropriate”.


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A April2002 Release v1.5
Revision B September2002 Release v1.6
Revision C February2003 Release v1.6.1
Revision D September2003 Release v1.6.1 for RVDS v2.0
Revision E January2004 Release v1.7 for RVDS v2.1
Revision F December2004 Release v1.8 for RVDS v2.2
Revision G May2005 Release v1.8 SP1 for RVDS v2.2 SP1
Revision H March2006 Release v3.0 for RVDS v3.0
Revision I March2007 Release v3.1 for RVDS v3.1
Copyright © 2002-2007 ARM Limited. All rights reserved. ARM DUI 0182I