RealView Debugger Target Configuration Guide: B.4.5. Cortex-R4 peripheral register mapping

B.4.5. Cortex-R4 peripheral register mapping

Table B.20 shows the peripheral register mapping for the Cortex-R4 model (see Figure B.4). The functional peripherals are two UARTs, one Timer, a Watchdog, RTC, System Control, NVIC, TrustZone Interrupt Controller (TZIC), and General Interrupt Controller (GIC). These peripherals are described in the following sections. All other peripherals are represented by a basic register array in the memory map regions 0x1nnnnnnn and 0xCnnnnnnn.

Note

Peripheral locations are accessible only when the MPU is enabled.

To access the peripheral registers, select the corresponding tab in the Registers view.

Table B.20. Cortex-R4 peripheral register mapping

Base Address	Peripheral
`0x10009000`	UART0 (Feature restricted)
`0x1000A000`	UART1
`0x10011000`	Timer
`0x10010000`	WDOG (Watchdog)
`0x10017000`	RTC (Real-Time Clock)
`0x10001000`	System Control (clock control for timers, configuration options, and remap signal)
Not applicable	NVIC (Nested Vectored Interrupt Controller)
`0x10040000`	TZIC (TrustZone Interrupt Controller)
`0x10050000`	GIC (General Interrupt Controller)

Primary Interrupt Controller

Table B.21 shows the PIC registers of the Cortex-R4 model.

Table B.21. Cortex-R4 PIC registers

Offset	Register
`0x00`	`PIC_IRQ_STATUS`
`0x04`	`PIC_IRQ_RAWSTAT`
`0x08`	`PIC_IRQ_ENABLE`
`0x10`	`PIC_INT_SOFTSET`
`0x14`	`PIC_INT_SOFTCLR`
`0x20`	`PIC_FIQ_STATUS`
`0x24`	`PIC_FIQ_RAWSTAT`
`0x28`	`PIC_FIQ_ENABLE`

Timers

Table B.22 shows the Timer registers of the Cortex-R4 model.

Table B.22. Cortex-R4 Timer registers

Offset	Register
`0x000`	`Timer0Load`
`0x018`	`Timer0BGLoad`
`0x004`	`Timer0Value`
`0x008`	`Timer0Control`
`0x00C`	`Timer0IntClr`
`0x010`	`Timer0RIS`
`0x014`	`Timer0MIS`
`0x100`	`Timer1Load`
`0x118`	`Timer1BGLoad`
`0x104`	`Timer1Value`
`0x108`	`Timer1Control`
`0x10C`	`Timer1IntClr`
`0x110`	`Timer1RIS`
`0x114`	`Timer1MIS`
`0x200`	`Timer2Load`
`0x218`	`Timer2BGLoad`
`0x204`	`Timer2Value`
`0x208`	`Timer2Control`
`0x20C`	`Timer2IntClr`
`0x210`	`Timer2RIS`
`0x214`	`Timer2MIS`
`0xFE0`	`Timer_PeriphIDO`
`0xFE4`	`Timer_PeriphID1`
`0xFE8`	`Timer_PeriphID2`
`0xFEC`	`Timer_PeriphID3`
`0xFF0`	`Timer_PCellIDO`
`0xFF4`	`Timer_PCellID1`
`0xFF8`	`Timer_PCellID2`
`0xFFC`	`Timer_PCellID3`

The three timers count down by only one tick for each instruction executed. The timers are mapped to the same memory locations as the timers on the Integrator™/CP development board.

Note

The Timer_PCellID and Timer_PeripID registers are not supported, but this does not affect the operation of the peripheral because it conforms to the ARM Generic Peripheral specification for Timers.

Real-Time Clock (PL030)

Table B.23 shows the RTC registers of the Cortex-R4 model.

Table B.23. Cortex-R4 RTC registers

Offset	Register
`0x000`	`RTC_DR`
`0x004`	`RTC_MR`
`0x008`	`RTC_STAT`
`0x00C`	`RTC_CLR`
`0x010`	`RTC_CR`
`0xFE0`	`RTC_PeriphIDO`
`0xFE4`	`RTC_PeriphID1`
`0xFE8`	`RTC_PeriphID2`
`0xFEC`	`RTC_PeriphID3`
`0xFF0`	`RTC_PCellIDO`
`0xFF4`	`RTC_PCellID1`
`0xFF8`	`RTC_PCellID2`
`0xFFC`	`RTC_PCellID3`

UART (PL011)

Table B.24 shows the UART0 and UART1 registers of the Cortex-R4 model.

Table B.24. Cortex-R4 UART registers

Offset	Register
`0x000`	`UARTDR`
`0x004`	`UARTRSR_ECR`
`0x018`	`UARTFR`
`0x020`	`UARTILPR`
`0x024`	`UARTIBRD`
`0x028`	`UARTFBRD`
`0x02C`	`UARTLCR_H`
`0x030`	`UARTCR`
`0x034`	`UARTIFLS`
`0x038`	`UARTIMSC`
`0x03C`	`UARTRIS`
`0x040`	`UARTMIS`
`0x044`	`UARTICR`
`0x048`	`UARTDMACR`
`0xFE0`	`UARTPeriphID0`
`0xFE4`	`UARTPeriphID1`
`0xFE8`	`UARTPeriphID2`
`0xFEC`	`UARTPeriphID3`
`0xFF0`	`UARTPCellID0`
`0xFF4`	`UARTPCellID1`
`0xFF8`	`UARTPCellID2`
`0xFFC`	`UARTPCellID3`

The Cortex-R4 models two serial ports that can be used for I/O. These are modeled through telnet windows, which open automatically on the first read/write operation from the UART after it has been initialized.

The serial ports are mapped to the same memory locations as the UARTs on the Integrator/CP development board.

Note

The default behavior for the telnet protocol is line mode. This means that characters typed into the telnet window are not seen in the model until you press Enter. To change this behavior type the telnet escape character, usually Ctrl+], and then enter the mode character. Doing this might disable local echo of the characters entered in the telnet window.

Interrupts

Table B.25 shows the supported interrupts for the Cortex-R4 model.

Table B.25. Cortex-R4 interrupts

Interrupt	Peripheral
1	UART0
2	UART1
3	Reserved
4	Reserved
5	Timer0
6	Timer1
7	Timer2
8	Reserved

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B.4.5. Cortex-R4 peripheral register mapping

Note

Primary Interrupt Controller

Timers

Note

Real-Time Clock (PL030)

UART (PL011)

Note

Interrupts

See also