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| Home > ISSM Configuration Reference > Cortex-M3 model configuration > Summary of supported features for the Cortex-M3 model |
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The following features are supported by Cortex-M3 model:
The Cortex-M3 model can execute all the instructions supported by Cortex-M3 processor.
Execution performance is a minimum of 3 MIPS on a 2GHz Intel workstation.
The behavior of the Nested Vectored Interrupt Controller (NVIC), MPU, Flash Patch and Breakpoint unit (FPB) and bus-matrix are modeled.
The model includes the following peripherals:
one UART
three Timers
Interrupt Controller (provided by the NVIC).
On reset, the model behaves similar to hardware.
Therefore, initial SP and PC values must be loaded at address 0x0,
followed by system-handler/interrupt vectors. An example is provided
in the following directory to illustrate the use of the SP/PC addresses
and Cortex-M3 libraries:
install_directory\RVDS\Examples\...\...\platform\Cortex-M3
Cycle and instruction counting are supported.
Cortex-M3 Technical Reference Manual.
| Copyright © 2002-2009 ARM Limited. All rights reserved. | ARM DUI 0182K |
| Non-Confidential | |
| PDF version | |
| Home > ISSM Configuration Reference > Cortex-M3 model configuration > Summary of supported features for the Cortex-M3 model |