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B.3.6. Cortex-M3 peripheral register mapping

Table B.15 shows the peripheral register mapping for the Cortex-M3 model (see Figure B.3). The functional peripherals are three Timers and one UART. These peripherals are described in the following sections.

To access the peripheral registers, select the corresponding tab in the Registers view.

Table B.15. Cortex-M3 peripheral register mapping

AddressPeripheral
0x40018000 - 0x40018FFFPeripheral Bus out (UART)
0x40050000 - 0x4005FFFFPeripheral Bus out (Timer)

Note

The rest of the peripheral memory space is unimplemented.

Timers

Table B.16 shows the Timer registers of the Cortex-M3 model.

Table B.16. Cortex-M3 Timer registers

OffsetRegister
0x000TimerLoad0
0x004TimerValue0
0x008TimerControl0
0x00CTimerIntClr0
0x010TimerRIS0
0x014TimerMIS0
0x018TimerBGLoad0
0x100TimerLoad1
0x104TimerValue1
0x108TimerControl1
0x10CTimerIntClr1
0x110TimerRIS1
0x114TimerMIS1
0x118TimerBGLoad1
0x200TimerLoad2
0x204TimerValue2
0x208TimerControl2
0x20CTimerIntClr2
0x210TimerRIS2
0x214TimerMIS2
0x218TimerBGLoad2
0xFE0Timer PeriphIDO
0xFE4Timer PeriphID1
0xFE8Timer PeriphID2
0xFECTimer PeriphID3
0xFF0Timer PCellIDO
0xFF4Timer PCellID1
0xFF8Timer PCellID2
0xFFCTimer PCellID3

The three timers count down by only one tick for each instruction executed. The timers are mapped to the same memory locations as the timers on the Integrator™/CP development board.

Note

The NVIC timer counts one tick per notional cycle. This differs from the other per instruction timers, for example, for LDM and STM instructions.

Note

The Timer PCellIDn and Timer PeripIDn registers are not supported, but this does not affect the operation of the peripheral because it conforms to the ARM Generic Peripheral specification for Timers.

UART

Table B.17 shows the UART registers of the Cortex-M3 model.

Table B.17. Cortex-M3 UART registers

OffsetRegister
0x000UARTDR
0x004UARTRSR_ECR
0x018UARTFR
0x020UARTILPR
0x024UARTIBRD
0x028UARTFBRD
0x02CUARTLCR_H
0x030UARTCR
0x034UARTIFLS
0x038UARTIMSC
0x03CUARTRIS
0x040UARTMIS
0x044UARTICR
0x048UARTDMACR
0xFE0UARTPeriphID0
0xFE4UARTPeriphID1
0xFE8UARTPeriphID2
0xFECUARTPeriphID3
0xFF0UARTPCellID0
0xFF4UARTPCellID1
0xFF8UARTPCellID2
0xFFCUARTPCellID3

The Cortex-M3 models one serial port that can be used for I/O. This is modeled through a telnet window, which opens automatically on the first read/write operation from the UART after it has been initialized.

The serial port is mapped to the same memory location as the UART on the Integrator/CP development board.

Note

The default behavior for the telnet protocol is line mode. This means that characters typed into the telnet window are not seen in the model until you press Enter. To change this behavior type the telnet escape character, usually Ctrl+], and then enter the mode character. Doing this might disable local echo of the characters entered in the telnet window.

Interrupts

Table B.18 shows the supported interrupts for the Cortex-M3 model.

Table B.18. Cortex-M3 interrupts

InterruptPeripheral
1UART
5Timer0
6Timer1
7Timer2

See also

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