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| Home > ISSM Configuration Reference > Cortex-M1 model configuration > Summary of supported features for the Cortex-M1 model |
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| Home > ISSM Configuration Reference > Cortex-M1 model configuration > Summary of supported features for the Cortex-M1 model | |||
The following features are supported by the Cortex-M1 model:
The Cortex-M1 model can execute all the Thumb-1 (THUMBv3) instructions supported by Cortex-M1 processor.
Execution performance is a minimum of 6 MIPS on a 2GHz Intel workstation.
The model includes the following peripherals:
one UART
three Timers
Nested Vectored Interrupt Controller (NVIC).
Tightly-Coupled Memory (TCM) components are supported as separate memory spaces with configurable size.
On reset, the model behaves similar to hardware.
Therefore, initial SP and PC values must be loaded at address 0x00000000,
followed by system handler and interrupt vectors. An example is
provided in the following directory to illustrate the use of the
SP/PC addresses and Cortex-M1 libraries:
install_directory\RVDS\Examples\...\...\...\platform\Cortex-M1
| Copyright © 2002-2009 ARM Limited. All rights reserved. | ARM DUI 0182K |
| Non-Confidential | |
| PDF version | |
| Home > ISSM Configuration Reference > Cortex-M1 model configuration > Summary of supported features for the Cortex-M1 model |