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The Cortex-M0 model has the following limitations:
The FPB and DWT debug components are not modeled.
Handling processor exceptions is not supported.
The debug and trace hardware is not modeled.
The halt-mode debug is not modeled. Consequently,
using BKPT results in the model stopping for the following
conditions:
when semihosting_enabled is False
when semihosting_enabled is True and
the BKPT immediate value does not match the semihosting_BKPT value.
In both cases, the following error message is displayed:
[core] Simulation terminated:
Using BKPT for halt-debug is unsupported
Lockup conditions are modeled as end-of-simulation conditions. This is because the model system does not include any peripherals to detect and correct these exception cases. See the section that describes unrecoverable exception cases in the ARMv6-M Architecture Reference Manual.
Late-arrival preemption and tail chaining are not modeled. This is because exception entry and exit are modeled as atomic transitions. Therefore, it is impossible for an asynchronous exception to be delivered within exception entry. See the section that describes exceptions on exception entry in the ARMv6-M Architecture Reference Manual.
| Copyright © 2002-2010 ARM Limited. All rights reserved. | ARM DUI 0182M |
| Non-Confidential | ID102410 |
| PDF version | |
| Home > ISSM Configuration Reference > Cortex-M0 model configuration > Limitations of the Cortex-M0 model |