RealView® Debugger Target Configuration Guide

Version 4.1


Table of Contents

Preface
About this book
Intended audience
Examples
Using this book
Typographical conventions
Further reading
Feedback
Feedback on this product
Feedback on this book
1. Introduction
1.1. About connection configuration
1.1.1. What is connection configuration?
1.1.2. Connect to Target window
1.1.3. Connection Properties window
1.2. Default configuration files
1.2.1. Debug Configuration board file
1.2.2. Debug Configuration settings
1.2.3. DSTREAM and RealView ICE configuration files
1.2.4. RVISS configuration files
1.2.5. ISSM configuration files
1.2.6. SoC Designer configuration files
1.2.7. RTSM configuration files
1.2.8. Board/Chip Definition files
1.3. How configuration files are linked together
1.4. What the configuration files contain
1.5. Locating the configuration files
1.5.1. The install directory
1.5.2. The RealView Debugger home directory
1.5.3. The RealView Debugger search path
1.5.4. Saving and restoring connection properties
1.6. Summary of supplied BCD files
2. Customizing a Debug Interface configuration
2.1. About customizing a Debug Interface configuration
2.2. About customizing a DSTREAM or RealView ICE Debug Interface configuration
2.2.1. DSTREAM and RealView ICE device names for supported CoreSight components
2.2.2. Considerations when customizing DSTREAM or RealView ICE Debug Interface configurations
2.2.3. Recommended settings for an ARM Integrator development board
2.3. Customizing a DSTREAM or RealView ICE Debug Interface configuration for non-CoreSight development platforms
2.4. Customizing a DSTREAM or RealView ICE Debug Interface configuration for development platforms containing CoreSight components
2.5. Customizing an RVISS Debug Interface configuration
2.5.1. Procedure for customizing an RVISS Debug Interface configuration
2.5.2. Considerations when customizing RVISS Debug Interface configurations
2.6. Customizing an ISSM Debug Interface configuration
2.6.1. Procedure for customizing an ISSM Debug Interface configuration
2.6.2. Considerations when customizing an ISSM Debug Interface configuration
2.7. Customizing an RTSM Debug Interface configuration
2.7.1. Procedure for customizing an RTSM Debug Interface configuration
2.8. Customizing a Model Library Debug Interface configuration
2.8.1. Procedure for customizing a Model Library Debug Interface configuration
2.8.2. Considerations when customizing an Model Library Debug Interface configuration
2.9. Customizing a Model Process Debug Interface configuration
2.9.1. Procedure for customizing a Model Process Debug Interface configuration
2.9.2. Considerations when customizing an Model Process Debug Interface configuration
2.10. Customizing a SoC Designer Debug Interface configuration
2.10.1. Procedure for customizing a SoC Designer Debug Interface configuration (SoC Designer not running)
2.10.2. Procedure for customizing a SoC Designer Debug Interface configuration (SoC Designer running)
3. Customizing a Debug Configuration
3.1. About customizing a Debug Configuration
3.1.1. Relationship between connection properties and Debug Configurations
3.1.2. Managing configuration settings
3.1.3. Using the examples
3.2. Viewing the Connection Properties
3.2.1. Displaying the Connection Properties dialog box
3.2.2. Displaying the Connection Properties window
3.2.3. Identifying groups in the List of Entries pane
3.2.4. Identifying settings in the Settings Values pane
3.2.5. Debug Configuration entries
3.2.6. The Debug Configuration Advanced_Information block
3.3. Changing connection settings
3.3.1. Changing entries containing user-information values
3.3.2. Changing a specific value back to the default value
3.3.3. Changing the order of settings that have multiple values
3.3.4. Removing instances from multi-value settings
3.3.5. Avoiding conflicts between linked board groups
3.4. Loading a different board file
3.4.1. Manually loading a board file
3.4.2. Forcing the load of a specific board file on startup (global configuration)
3.4.3. Forcing the load of a specific board file on startup (workspace configuration)
3.5. Hiding a Debug Configuration
3.6. Specifying connect and disconnect mode
3.6.1. Configuring connect mode
3.6.2. Configuring disconnect mode
3.7. Creating a target-specific Advanced_Information group
3.8. Configuring vector catch
3.8.1. Default settings for processor exceptions
3.8.2. Setting vector catch for all targets
3.8.3. Setting vector catch for individual targets
3.8.4. Temporarily overriding the vector catch for an existing connection
3.8.5. Considerations when setting SVC vector catch (hardware targets)
3.9. Configuring Semihosting
3.9.1. Configuring semihosting for all targets
3.9.2. Configuring semihosting for individual targets
3.9.3. Considerations when configuring semihosting
3.10. Configuring the CLI commands for hardware cross-triggering
3.11. Configuring a connection sequence for multiple targets
3.11.1. Setting a generic connection sequence for a Debug Configuration
3.11.2. Specifying a target-specific connection sequence
3.12. Running CLI commands automatically on connection
3.13. Configuring RealMonitor for connections through DSTREAM or RealView ICE
3.13.1. Restrictions on using RealMonitor with DSTREAM or RealView ICE
3.13.2. Rules for connecting DSTREAM or RealView ICE to a running target
3.13.3. Basic procedure
3.13.4. Customizing the Debug Configuration used for enabling RealMonitor
3.13.5. Customizing the Debug Configuration used for debugging with RealMonitor
3.13.6. Loading an image before using RealMonitor
3.13.7. Working with RealMonitor
3.14. Flash programming
3.14.1. Requirements for programming Flash
3.15. Using the Thumb-2EE helper macro
3.15.1. Loading the Thumb-2EE helper macro for a single processor system
3.15.2. Loading the Thumb-2EE helper macro for a multiprocessor system
3.15.3. Using the Thumb-2EE helper macro with breakpoints and tracepoints
3.15.4. Examining the definition of the handleraddr() macro
3.16. Restoring the default connections and configurations
3.17. Preparing Debug Configurations for distribution
3.18. Distributing Debug Configurations to other machines and users
3.18.1. Considerations when distributing Debug Configurations
3.19. Example of setting up an Integrator board and processor core module
3.19.1. Setting up the hardware and Debug Interface
3.19.2. Creating the new Debug Configuration
3.19.3. Configuring the new Debug Configuration
3.19.4. Linking board groups to the new Debug Configuration
3.19.5. Connecting to the new target
3.19.6. Viewing the new target definition
3.20. Troubleshooting Debug Configurations
3.20.1. Problems with target-specific settings
3.20.2. Problems with missing or corrupt configuration files
3.20.3. Debug Configuration reports a General Error status
4. Configuring Custom Memory Maps, Registers and Peripherals
4.1. About configuring custom memory maps, registers, and peripherals
4.1.1. BCD file configuration entries
4.1.2. The board/chip definition Advanced_Information block
4.1.3. Board, chip, and component groups
4.1.4. Suggested naming convention for memory map related settings groups
4.1.5. Using the examples
4.2. Assigning a board, chip, or component group to a Debug Configuration
4.2.1. Assigning one board group to a Debug Configuration
4.2.2. Assigning several board groups to a Debug Configuration
4.2.3. Assigning one or more board groups to another board group
4.2.4. Assigning one or more board groups to a multiprocessor Debug Configuration
4.3. Using the supplied BCD files
4.4. Creating a BCD file to use as a template
4.5. Basic procedure for creating BCD files
4.5.1. Managing configuration settings
4.6. Creating a new BCD file
4.7. Creating and naming a board, chip, or component group
4.7.1. Adding a new board/chip definition
4.7.2. Renaming a board/chip definition
4.8. Assigning board/chip definitions
4.8.1. Assigning a board/chip definition to a Debug Configuration
4.8.2. Assigning a board/chip definition to another board/chip definition
4.8.3. Assigning multiple board/chip definitions to a Debug Configuration
4.9. Setting top of memory
4.9.1. About top of memory, stack and heap
4.9.2. Examining the top of memory value
4.9.3. Setting top of memory
4.10. Creating a memory map block
4.10.1. Preparing the configuration
4.10.2. Procedure for creating a memory map block
4.10.3. Creating a memory map block that relates to custom registers and peripherals
4.10.4. Viewing the memory map block
4.11. Creating an enumeration for setting register values
4.12. Creating a custom memory mapped register
4.12.1. Creating the custom register
4.12.2. Defining a separate bit field for a custom register
4.13. Creating a custom peripheral
4.13.1. Creating the custom peripheral
4.13.2. Creating the registers for a custom peripheral
4.13.3. Defining separate bit fields for a custom peripheral register
4.14. Creating the register tab for displaying custom registers and peripherals
4.14.1. Viewing the custom registers and peripherals
4.15. Creating memory map rules
4.16. Setting up controlled memory blocks
4.16.1. Before you set up controlled memory blocks
4.16.2. Defining the controlled memory map blocks
4.16.3. Defining the memory rules
4.16.4. Displaying the controlled memory map blocks
4.17. Creating a concatenated register
4.17.1. Viewing the concatenated register
4.18. Troubleshooting BCD files
4.18.1. Expected memory map is not displayed
4.18.2. Expected register tab does not appear in the Registers view
4.18.3. Duplicate definition warning messages on connecting
4.18.4. Overlapping un-controlled memory region warning messages on connecting
4.18.5. Map-Rule and Undefined register warnings
5. Debug Configuration Tutorial
5.1. About the Debug Configuration tutorial
5.1.1. About the development platform used in this tutorial
5.2. Before starting the tutorial
5.3. Creating a new Debug Configuration
5.4. Configuring the new Debug Configuration
5.5. Creating the EtherRouter.bcd file
5.6. Creating the AMDLANCE.bcd file
5.7. Creating the EtherRouter BOARD group
5.8. Creating the AMDLANCE CHIP group
5.9. Assigning board/chip definitions
5.9.1. Assigning the EtherRouter board/chip definition to a Debug Configuration
5.9.2. Assigning the AMDLANCE and KS32C50100 chips to the EtherRouter board
5.10. Creating the memory map
5.10.1. Creating the M_IO_REGS memory map block
5.10.2. Creating the M_I2C memory map block
5.10.3. Viewing the memory map
5.11. Creating the enumerations for the register values
5.12. Creating a custom register
5.12.1. Creating the custom register
5.12.2. Defining the bit fields for the custom register
5.13. Creating the register tab for displaying custom registers
5.13.1. Defining the visual appearance of the custom registers
5.13.2. Viewing the custom registers
5.14. Setting up controlled memory map blocks
5.15. Creating memory map rules
5.16. Displaying the controlled memory map blocks
5.17. Creating a concatenated register
5.17.1. Creating the C_R8_R9_concat concatenated register
5.17.2. Viewing the concatenated register
6. Programming Flash with RealView Debugger
6.1. Introduction to Flash programming with RealView Debugger
6.1.1. Summary of files used to program Flash on supported development platforms
6.1.2. Summary of files used to program custom Flash types on custom platforms
6.2. RealView Debugger files used for Flash programming
6.2.1. Flash-level code
6.2.2. Board-level code
6.2.3. ASCII MEthod file
6.2.4. Flash MEthod file
6.2.5. Board Chip Definition file
6.3. pakflash utility command syntax
6.4. Programming Flash on the ARM development boards
6.4.1. About the ARM Integrator/AP board
6.4.2. Assigning a BCD file to a Debug Configuration
6.4.3. Reviewing the information contained in the Integrator/AP BCD file
6.4.4. Displaying the memory map in the Process Control view
6.4.5. Programming an image into Flash on the Integrator/AP
6.5. Programming Flash for a custom development platform
6.5.1. Third-party support for ARM processor-based development platforms
6.5.2. Programming a Flash type supported by RealView Debugger
6.5.3. Programming a custom Flash type
6.6. Gathering information about your development platform
6.6.1. Evaluator-7T example
6.7. Creating algorithms for a Flash type supported by RealView Debugger
6.7.1. The b_flashwrapper.s template file
6.7.2. Editing b_flashwrapper.s
6.7.3. Settings for the Evaluator-7T
6.8. Creating algorithms for a Flash type not provided with RealView Debugger
6.8.1. Basic Procedure
6.8.2. C source file containing the Flash-specific C functions
6.8.3. C header file
6.8.4. Assembly wrapper
6.9. Creating the Flash-level and board-level AME files
6.9.1. Flash-level AME file format
6.9.2. Board-level AME file format
6.10. Generating the FME file
6.10.1. Locating the source and AME files required
6.10.2. Specifying the compiler options
6.10.3. Specifying the assembler options
6.10.4. Specifying the linker options
6.10.5. Running the pakflash utility
6.11. Checking the FME file with the dispflash utility
6.11.1. Evaluator-7T example
6.12. Creating a BCD file
6.12.1. Basic procedure for the Evaluator-7T example
6.12.2. Saving a copy of the template BCD file
6.12.3. Creating the BOARD group in the BCD file
6.12.4. Describing the memory map
6.12.5. Assigning your board/chip definitions to a Debug Configuration
6.12.6. Viewing the memory map
6.13. Programming an image into Flash
6.13.1. Writing the image to Flash
6.13.2. Using CLI commands to program Flash
6.13.3. Checking the contents of Flash
6.14. Troubleshooting
A. Connection Properties Reference
A.1. About connection properties reference
A.1.1. The CONNECTION group
A.1.2. The DEVICE group
A.1.3. The BOARD, CHIP, and COMPONENT groups
A.1.4. Relationship between connections, boards, and chips
A.2. Debug Configuration generic groups and settings
A.2.1. Connect_with
A.2.2. Remote
A.2.3. Advanced_Information block (base group)
A.2.4. Configuration
A.2.5. Auto_connect
A.2.6. Pre_connect
A.2.7. Description
A.2.8. Project
A.2.9. Disabled
A.2.10. Shared
A.2.11. BoardChip_name
A.2.12. Family_select
A.3. Debug Configuration Advanced_Information settings reference
A.3.1. Application_Load
A.3.2. ARM_config settings for a Debug Configuration
A.3.3. Logic_Analyzer
A.3.4. Cross_trigger
A.3.5. RTOS_config
A.3.6. Monitor
A.3.7. Pre_connect
A.3.8. Commands
A.3.9. Connect_mode
A.3.10. Disconnect_mode
A.3.11. Id_chip
A.3.12. Id_match
A.3.13. Chip_name
A.3.14. Endianess
A.3.15. Sw_bkpts
A.4. Memory mapping Advanced_Information settings reference
A.4.1. ARM_config settings related to memory mapping
A.4.2. Memory_block
A.4.3. Map_rule
A.4.4. Register_enum
A.4.5. Register
A.4.6. Concat_Register
A.4.7. Peripherals
A.4.8. Register_Window
B. ISSM Configuration Reference
B.1. Cortex-A8 model configuration
B.1.1. Summary of supported features for the Cortex-A8 model
B.1.2. Limitations of the Cortex-A8 model
B.1.3. Cortex-A8 configuration parameters
B.1.4. Cortex-A8 memory map
B.1.5. Cortex-A8 peripheral register mapping
B.2. Cortex-M0 model configuration
B.2.1. Summary of supported features for the Cortex-M0 model
B.2.2. Limitations of the Cortex-M0 model
B.2.3. Cortex-M0 configuration parameters
B.2.4. Cortex-M0 memory map
B.2.5. Cortex-M0 peripheral register mapping
B.3. Cortex-M1 model configuration
B.3.1. Summary of supported features for the Cortex-M1 model
B.3.2. Considerations when using the Cortex-M1 model
B.3.3. Limitations of the Cortex-M1 model
B.3.4. Cortex-M1 configuration parameters
B.3.5. Cortex-M1 memory map
B.3.6. Cortex-M1 peripheral register mapping
B.4. Cortex-M3 model configuration
B.4.1. Summary of supported features for the Cortex-M3 model
B.4.2. Limitations of the Cortex-M3 model
B.4.3. Cycle and instruction counting feature
B.4.4. Cortex-M3 configuration parameters
B.4.5. Cortex-M3 memory map
B.4.6. Cortex-M3 peripheral register mapping
B.5. Cortex-R4 model configuration
B.5.1. Summary of supported features for the Cortex-R4 model
B.5.2. Limitations of the Cortex-R4 model
B.5.3. Cortex-R4 configuration parameters
B.5.4. Cortex-R4 memory map
B.5.5. Cortex-R4 peripheral register mapping

List of Figures

1.1. Relationships in the Connect to Target window
1.2. Example Connect to Target window
1.3. Example Connection Properties window
1.4. Relationship between configuration files
2.1. DSTREAM and RealView ICE Debug Interfaces in the Connect to Target window
2.2. ARMulator configuration dialog box
2.3. Model Configuration Utility dialog box
2.4. Model Configuration Utility dialog box (RTSM)
2.5. Model Configuration Utility dialog box
3.1. Relationship between Connection Properties and the Connect to Target window
3.2. Connection Properties dialog box
3.3. Connection Properties window
3.4. RealMonitor Debug Configuration for debugging
3.5. RealMonitor Debug Configuration for running target
3.6. Debug Configuration settings
3.7. New Debug Configuration added
3.8. Displaying the new MP3Player connection properties
3.9. Connecting to the new target
3.10. AP tab in the Registers view
4.1. Viewing .bcd files in the Connection Properties window
4.2. Assigning one board to a connection
4.3. Assigning two boards to a Debug Configuration
4.4. Board and chip groups for the Evaluator-7T
4.5. Tree view of the assigned groups in the Eval7T.bcd file
4.6. Board and chip groups for the EtherRouter board
4.7. Tree view of the assigned groups for the EtherRouter board
4.8. Customizing a two-processor Debug Configuration
4.9. Referencing two .bcd files in the Connection Properties window
4.10. Connection Properties window
4.11. Saving an existing BCD file with a new name
4.12. Viewing the new group in the BCD file
4.13. Assigning the KS32C50100 group
4.14. Relating top_of_memory to single section program layout
4.15. Connection Properties for the RealView-ICE Debug Configuration
4.16. CM940T BOARD group selected
4.17. Viewing the contents of the new group
4.18. Configuring M_REGS
4.19. New memory map block in the Process Control view
4.20. Memory map with image loaded
4.21. Creating enumerations
4.22. Creating bit field for registers
4.23. Creating bit fields for peripheral registers
4.24. Register_Window group
4.25. The MP3_REGS group
4.26. MP3_REGS tab in the Registers view
4.27. Settings for the R_FastRAM map rule
4.28. Settings for the R_SlowROM map rule
4.29. Settings for the R_FastRAM map rule
4.30. Settings for the R_SlowROM map rule
4.31. MP3_REGS tab in the Registers view
4.32. New memory block in the Memory Map tab
4.33. Activated ROM memory block in the Memory Map tab
4.34. Concat_reg tab in Registers view
4.35. User view showing concatenated register
4.36. User view showing concatenated register values
4.37. Memory map defined in the CM926EJ-S.bcd file
4.38. Combined memory map for CM926EJ-S and CP board/chip definitions
5.1. Linked groups for the EtherRouter board
5.2. Tree view of the linked groups
5.3. RVISS_3 Debug Configuration in the Connect to Target window
5.4. Connection Properties for the EtherRouter Debug Configuration
5.5. Saving an existing BCD file with a new name
5.6. Connection properties for the RVI Debug Configuration
5.7. Assigning the EtherRouter BCD group
5.8. Setting up the EtherRouter.bcd
5.9. Configuring the M_IO_REGS custom register
5.10. Configuring the M_I2C custom register
5.11. New memory map in the Process Control view
5.12. Memory map with dhrystone image loaded
5.13. Creating enumerations
5.14. Creating bit field for a custom register
5.15. The EtherRouter Register_window group
5.16. EtherRouter tab in the Registers view
5.17. M_FastRAM memory block
5.18. M_SlowROM memory block
5.19. Settings for the R_Fast_RAM map rule
5.20. Settings for the R_SlowROM map rule
5.21. EtherRouter tab in the Registers view
5.22. RAM memory block in the Memory Map tab
5.23. Activated ROM memory block in the Memory Map tab
5.24. Core tab shown in the Registers view
5.25. Concatenated register in EtherRouter tab
5.26. User view showing the concatenated registers
5.27. User view showing concatenated register values
6.1. New memory map in the Process Control view
6.2. The Flash Memory Control dialog box
6.3. Flash programming complete
6.4. Flash image details in memory map
6.5. Viewing the new memory map
A.1. How connections, boards, and chips fit together
A.2. Viewing generic settings for a Debug Configuration
B.1. Cortex-A8 memory map
B.2. Cortex-M0 memory map
B.3. Cortex-M1 memory map
B.4. Cortex-M3 memory map
B.5. Cortex-R4 memory map

List of Tables

1.1. Supported Debug Interfaces
1.2. Default values for common connection attributes
2.1. DSTREAM and RealView ICE device names for CoreSight Components
2.2. Recommended settings for an ARM Integrator development board
2.3. RealView ARMulator ISS Endian settings 
3.1. Action performed after reset
3.2. Default settings for Processor Exceptions
3.3. CLI commands to enable and disable the ARM966E-S In and Out triggers
3.4. Bit fields use for cross-triggering on ARM966E-S
3.5. Connect sequence using the generic Pre_connect setting
3.6. Pre_connect settings in Advanced_Information block
3.7. Connection sequence using target-specific Pre_connect setting
3.8. Pre_connect settings in Advanced_Information block
3.9. DSTREAM or RealView ICE settings for RealMonitor
3.10. Default configuration files in the home directory
4.1. Suggested naming convention
4.2. Additional bitfields
4.3. C_R8_R9_concat settings
5.1. R8_R9_concat settings
6.1. Files used to program Flash on supported development platforms
6.2. Evaluator-7T memory map
6.3. Evaluator-7T example settings
6.4. Memory map attributes
B.1. Cortex-A8 model configuration parameters
B.2. Cortex-A8 peripheral register mapping
B.3. Cortex-A8 PIC registers
B.4. Cortex-A8 RTC registers
B.5. Cortex-A8 Timer registers
B.6. Cortex-A8 UART registers
B.7. Cortex-A8 interrupts
B.8. Cortex-M0 model configuration parameters
B.9. Cortex-M0 peripheral register mapping
B.10. Cortex-M0 Timer registers
B.11. Cortex-M0 UART registers
B.12. Cortex-M0 interrupts
B.13. Cortex-M1 model configuration parameters
B.14. Cortex-M1 peripheral register mapping
B.15. Cortex-M1 Timer registers
B.16. Cortex-M1 UART registers
B.17. Cortex-M1 interrupts
B.18. Cortex-M3 cycle count registers and symbols
B.19. Cortex-M3 model configuration parameters
B.20. Cortex-M3 peripheral register mapping
B.21. Cortex-M3 Timer registers
B.22. Cortex-M3 UART registers
B.23. Cortex-M3 interrupts
B.24. Cortex-R4 model configuration parameters
B.25. Cortex-R4 peripheral register mapping
B.26. Cortex-R4 PIC registers
B.27. Cortex-R4 Timer registers
B.28. Cortex-R4 RTC registers
B.29. Cortex-R4 UART registers
B.30. Cortex-R4 interrupts

Proprietary Notice

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Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AApril 2002Release v1.5
Revision BSeptember 2002Release v1.6
Revision CFebruary 2003Release v1.6.1
Revision DSeptember 2003Release v1.6.1 for RealView Developer Suite v2.0
Revision EJanuary 2004Release v1.7 for RealView Developer Suite v2.1
Revision FDecember 2004Release v1.8 for RealView Developer Suite v2.2
Revision GMay 2005Release v1.8 SP1 for RealView Developer Suite v2.2 SP1
Revision HMarch 2006Release v3.0 for RealView Development Suite v3.0
Revision IMarch 2007Release v3.1 for RealView Development Suite v3.1
Revision JSeptember 2008Release v4.0 for RealView Development Suite v4.0
Revision K27 March 2009Release v4.0.1 for RealView Development Suite v4.0
Revision L28 May 2010Release 4.1 for RealView Development Suite v4.1
Revision M30 September 2010Release 4.1 SP1 for RealView Development Suite v4.1 SP1
Copyright © 2002-2010 ARM Limited. All rights reserved.ARM DUI 0182M
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