A.3.2. ARM_config settings for a Debug Configuration

This group enables control of ARM processor settings used for ARM emulators, monitors, or simulators. These control features such as semihosting and vector catching, which must be set or unset depending on the type of runtime you have linked into your application.


Although this group contains settings for memory control, only the semihosting and vector catch settings must be set in a Debug Configuration CONNECTION group.

You can also set many of these at runtime using pseudo-registers. To do this, use an Advanced_Information block named Default if it applies to all devices or create a block with a name of the scan chain device to which it applies.

ARM_config group settings

The following settings in the ARM_config group must be set only in a Debug Configuration CONNECTION group:


If Vector_catch is set to True, the fields within this group enable individual control over each vector. They are used to catch possible program errors by setting breakpoints on (or otherwise trapping) the vectors. The default is to catch error-type vectors, but not IRQ, FIQ and SVC. SVC is caught separately by semihosting if enabled. The vectors must be writable.

The Vectors group contains:


Set this to catch Reset exceptions.


Set this to catch undefined instruction exceptions.


Set this to catch SuperVisor Call (SVC) exceptions.


Set this to catch Prefetch abort exceptions.


Set this to catch Data abort exceptions.


Set this to catch Address exceptions. Used only by the obsolete 26-bit ARM processor architectures.


Set this to catch normal interrupt exceptions.


Set this to catch Fast Interrupt exceptions.


Set this to catch errors on RealView ARMulator® ISS (RVISS) targets only.

You can also set these during debugging as follows:

  • Select Processor Exceptions... from the Code window Debug menu to open the Processor Exceptions dialog box.

  • Use the BGLOBAL CLI command.

  • Use the following pseudo-registers:

    • @vector_catch for hardware connections

    • the @semihost_vector_catch pseudo-register for connections through RVISS.

    Bits 0 to 8 of these pseudo-registers represent the vectors from Reset to Error, respectively.


For non ARMv7-M processors with the semihosting vector set to the default (0x8), you must not enable the SVC vector catch if semihosting is enabled.


Enables programs to communicate with the host workstation. Semihosting operations supported include stack and heap assignment and console I/O (printf and scanf type calls). Semihosting is implemented using the SVC instruction. You can change the semihosting vector during debug using the @semihost_vector pseudo-register.

On some targets you can also define a window or file number to display semihosting printf messages using setreg @SEMIHOST_WINDOW=number. A window number must match a window opened with the VOPEN command, and a file number must match a file opened with the FOPEN command.


If your program requires direct user input, do not change the value. The default value identifies the StdIO tab of the Output view. Direct user input is possible only from this tab.

The Semihosting group contains:


Set this to enable semihosting.


For non ARMv7-M processors with the semihosting vector set to the default (0x8), you must not enable semihosting if the SVC vector catch is enabled.


Address of semihosting vector. For non ARMv7-M processors, this is the address of the SVC vector catch.


ARM SVC instruction for semihosting.


Thumb® SVC instruction for semihosting.




Clock speed in MHz as num.num.


True if floating point emulation.


The name of the configuration file.


When set to True, the fields within the Vectors group determine the which vectors are enabled.


This enables free-form definition of the properties required by a Debug Interface (emulator or simulator). The form of the string is name=value, where name is the name for the property as defined by the Debug Interface and value is a numeric value in hex or decimal.

See also

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