RealView Debugger Target Configuration Guide: B.5.3. Cortex-R4 configuration parameters

B.5.3. Cortex-R4 configuration parameters

Table B.24 describes the configuration parameters for the Cortex-R4 model.

Table B.24. Cortex-R4 model configuration parameters

Parameter	Description	Default
`cfgnmfi`	Configure non-maskable Fast Interrupts.	`False`
`dcachemax`	Encodings for the data cache maximum size: `0x0` 4KB `0x1` 8KB `0x3` 16KB `0x7` 32KB `0xf` 64KB	`0xF`
`dcachemin`	Encodings for the data cache minimum size: `0x0` 4KB `0x1` 8KB `0x3` 16KB `0x7` 32KB `0xf` 64KB	`0x0`
`dtcmsize`	Encodings for the DTCM size: `0x0` 0KB `0x3` 4KB `0x4` 8KB `0x5` 16KB `0x6` 32KB `0x7` 64KB `0x8` 128KB `0x9` 256KB `0xA` 512KB `0xB` 1MB `0xC` 2MB `0xD` 4MB `0xE` 8MB	`0xE`
`hivecs`	Let exception vectors start at `0xFFFF0000`.	`False`
`icachemax`	Encodings for the instruction cache maximum size: `0x0` 4KB `0x1` 8KB `0x3` 16KB `0x7` 32KB `0xf` 64KB	`0xF`
`icachemin`	Encodings for the instruction cache minimum size: `0x0` 4KB `0x1` 8KB `0x3` 16KB `0x7` 32KB `0xf` 64KB	`0x0`
`initee`	Set data endianness.	`False`
`initie`	Set instruction endianness.	`False`
`initramd`	Enable DTCM at reset.	`False`
`initrami`	Enable ITCM at reset.	`False`
`itcmsize`	Encodings for the ITCM size: `0x0` 0KB `0x3` 4KB `0x4` 8KB `0x5` 16KB `0x6` 32KB `0x7` 64KB `0x8` 128KB `0x9` 256KB `0xA` 512KB `0xB` 1MB `0xC` 2MB `0xD` 4MB `0xE` 8MB	`0xE`
`loczrami`	Set initial ITCM offset: `False` ITCM offset is `0x0` DTCM offset is `0x40000000` `True` ITCM offset is `0x40000000` DTCM offset is `0x0`	`False`
`mpuregions`	Number of MPU regions (0, 8, or 12)	`0xC`
`no_entcm1if`	Disable B1 TCM interface	`False`
`nodcache`	No Data Cache	`False`
`nofpu`	Support floating-point.	`False`
`noicache`	No Instruction Cache	`False`
`noie`	Disable big-endian instruction support	`False`
`randomfiq`	Enable random FIQ	`False`
`randomirq`	Enable random IRQ	`False`
`rmwenram`	Enable read-modify-write for TCM interfaces	`False`
`saveAndRestore-enable`	When disabled the model: can not save its state for a future session can not pick up a saved state from a previous session. There is a minimal overhead on the performance of the simulation when this is enabled.	`False`
`semihosting-ARM_SVC`	The ARM SVC used for semihosting. The value must be in the range 0 to 16777215 (`0xFFFFFF`).	`0x123456`
`semihosting-clock_frequency`	Simulated clock frequency in MHz, which uses the elapsed time based on the number of instructions executed. The value must be in the range 1 to 4294967295 (`0xFFFFFFFF`). Note The number you specify has no relationship to the hardware processor.	`0x32`
`semihosting-cmd_line`	Semihosting command line string used for passing command-line arguments to an image. Separate each argument with a space, and quote any arguments that include a space, for example: `argument1 "argument 2" argument_3`
`semihosting-debug`	Print verbose messages for semihosting.	`False`
`semihosting-enable`	Enable or disable semihosting.	`True`
`semihosting-Thumb_SVC`	The Thumb SVC used for semihosting. The value must be in the range 0 to 255 (`0xFF`).	`0xAB`
`semihosting-heap_base`	Semihosting heap base. The value must be in the range 0 to 4294967295 (`0xFFFFFFFF`).	`0x0`
`semihosting-heap_limit`	Semihosting heap limit. The value must be in the range 0 to 4294967295 (`0xFFFFFFFF`).	`0xF000000`
`semihosting-stack_base`	Semihosting stack base. The value must be in the range 0 to 4294967295 (`0xFFFFFFFF`).	`0x10000000`
`semihosting-stack_limit`	Semihosting stack limit. The value must be in the range 0 to 4294967295 (`0xFFFFFFFF`).	`0xF000000`
`sldtcmsb`	Use MSB of the address to select D1 TCM, otherwise bit[3].	`False`
`tcmhiinitaddr`	TCM High initialization address offset.	`0x40000000`
`teinit`	Exception handling state. Set processor to Thumb mode when entering an excpetion.	`False`
`warn-extra`	Print some useful additonal warning messages.	`False`
`warn-undefined`	Print a warning when an undefined instruction is hit.	`False`

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B.5.3. Cortex-R4 configuration parameters

Note