The PLD configuration is loaded into the PLD at power ON from the flash chip U8. The PLD configuration flash contains four images that are selected by the signals CFGSEL[1:0] from the motherboard or by using the image select switch. See PLD image selection.

The flash chip U8 is selected by the EBI0 chip select signal EBI_nCS0. During power ON, the first 32KB of this chip select region is mapped to begin address 0x0. The flash contains four PLD images, and image select switches or CFGSEL[1:0] signals are used to control the upper 2 address bits CFG_EBI_A[22:21]. This allows you to select which of the four images to appears at 0x0.

During normal operation the EBI0 area cannot be accessed. To reprogram this flash, you must put the core module in config mode or set S1[4] to ON. See Loading new PLD configurations.

The boot monitor is stored in flash in EBI1 (0x0F000000-0x0F7FFFFF). It is copied into the SRAM at startup. The boot configuration then jumps to the SRAM when boot monitor is run. To run the boot monitor you must set the switch S2[8] to ON, see Table 4.6.

The user area of the core module flash is in EBI2 (0x0F800000-0x0FFFFFFF). You can use this area to store your own data. The user area is write-protected by default. Before you can write to the flash you must drive EBI_WP HIGH. This signal must be controlled by logic in the PLD image.

The supplied PLD images provide a register location that allows you to control the EBI_WP signal. For more information about controlling this signal:

You can run the code in EBI1 or EBI2 at startup by setting switch S2[8:7] as shown in Table 4.6.