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| Home > IM-PD1 Image for Operation with an Integrator/IM-PD1 > CM control and status registers for the IM-PD1 image > Core module status register, CM_STAT |
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| Home > IM-PD1 Image for Operation with an Integrator/IM-PD1 > CM control and status registers for the IM-PD1 image > Core module status register, CM_STAT | |||
The core module status register at 0x10000010 is
a read-only register that can be read to determine the size of the
SSRAM present, the test chip type, and where in a stack this core
module is positioned.
Table 8.7 describes the core module status register bits.
Table 8.7. CM_STAT register
Bit | Name | Access | Function | Default |
|---|---|---|---|---|
[31:24] | USR_SW | Read | These are used to read the user switches. 1 = ON 0 = OFF. | - |
| [23:16] | SSRAMSIZE | Read | SSRAM size. | 00000100 |
| [15:8] | SI_ID | Read | Silicon manufacturer identification. Identifies the manufacturer and type of core fitted to the module. | 00000000 |
| [7:0] | ID | Read | Card number in stack: 0x00 = core module 0 0x01 = core module 1 0x02 = core module 2 0x03 = core module 3 0xFF = invalid or no motherboard attached. | - |
| Copyright © 2002-2003. All rights reserved. | ARM DUI 0184B |
| Non-Confidential | |
| PDF version | |
| Home > IM-PD1 Image for Operation with an Integrator/IM-PD1 > CM control and status registers for the IM-PD1 image > Core module status register, CM_STAT |