Integrator ™/CM922T-XA10 UserGuide

Core Module (HBI-0100)


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
ARM publications
Other publications
Feedback
Feedback on the core module
Feedback on this book
1. Introduction
1.1. About the Integrator/CM922T-XA10
1.2. Main features
1.2.1. Core module components
1.2.2. Altera Excalibur EPXA10 features
1.3. Core module connectors
1.4. Core module LEDs, switches, and links
1.4.1. LEDs
1.4.2. Switches
1.4.3. CONFIG link
1.5. Precautions
1.5.1. Ensuring safety
1.5.2. Preventing damage
1.5.3. Ensuring correct operation
2. Getting Started
2.1. Preparing the system hardware
2.1.1. Fitting an Integrator/IM-PD1onto the core module
2.1.2. Mounting the core moduleonto an Integrator/CP
2.1.3. Mounting the core moduleonto an Integrator/AP
2.1.4. Setting the modeswitch
2.1.5. Setting the generalpurpose/boot code switch
2.1.6. Connecting power
2.1.7. Connecting programmingand debug equipment to the Integrator/CM-XA10
2.2. Getting started with Boot monitor
2.2.1. Boot switcher
2.2.2. System startup for a standalone coremodule
2.2.3. System startup for other system configurations
2.3. Building and downloading an executableimage
3. Using Multi-ICE, ByteBlaster, and Trace
3.1. Configuring JTAG
3.1.1. Debug mode
3.1.2. Config mode
3.2. JTAG signal routing
3.2.1. Data path
3.2.2. Clock path
3.2.3. Module stacking options
3.2.4. JTAG signal descriptions
3.3. Embedded trace support
3.3.1. About using trace
3.3.2. Debug communicationsinterrupts
3.3.3. Trace interface description
3.4. Using ByteBlaster
3.5. Altera tool flow
3.5.1. Synthesis
3.5.2. Place and route
3.5.3. Compilation
3.6. Loading new PLD configurations
3.6.1. Downloading new PLD configurations into the image flash
3.6.2. Reconfiguring the PLD directly withJTAG
4. Integrator/CM922T-XA10 System Architecture
4.1. About the hardware architecture
4.2. About the Altera Excalibur EPXA10
4.2.1. Embedded core
4.2.2. Stripe memory and peripherals
4.2.3. Excalibur EPXA10 memory map
4.2.4. PLD image selection
4.2.5. PLD signal assignment
4.3. Integrator system bus
4.3.1. System bus signal routing
4.3.2. Signal assignments for connectorsHDRA and HDRB
4.3.3. Module-assignedsignals
4.3.4. Module ID selection
4.4. Expansion module interface EXPIM
4.5. Core module memory
4.5.1. Flash memory
4.5.2. Double Data Rate SDRAM
4.5.3. SSRAM
4.5.4. Optional SDRAM DIMM
4.5.5. SSRAM and SDRAM DIMMinterface signals
4.6. Core module clocks
4.6.1. Clock signal description
4.6.2. Clock control parameters
4.6.3. Clock programming interface
4.7. Reset architecture
4.7.1. Reset sequence
4.7.2. Reset signals
4.7.3. Software resets
4.8. Interrupt architecture
5. Basic Example Image for Simple Standalone Operation
5.1. About the basic example image
5.1.1. Selecting the basic example imageon your core module
5.1.2. Basic example imagefunctional block diagram
5.1.3. Basic example imagefunctional block HDL files
5.2. Basic example image memory map
5.3. Basic example image registers
5.3.1. Basic example ID register, BE_ID
5.3.2. Basic example processor register, BE_PROC
5.3.3. Oscillator divisor registers, BE_OSCx
5.3.4. User LEDs control register, BE_LEDs
5.3.5. User switch register, BE_SW
5.3.6. Reset register, BE_RST
5.4. Basic example imageclock control
5.4.1. Calculating theoutput frequencies of the ICS307
5.4.2. Basic example oscillatordivisor registers
6. CM Image for Operation Standalone or with an Integrator/AP
6.1. About the Integrator CM image
6.1.1. Selecting the CM image on a standalonecore module
6.1.2. Selecting the CM image on a core modulemounted on an Integrator/AP
6.1.3. CM image functionalblock diagram
6.1.4. The functional block HDL files
6.2. CM image memory map
6.3. CM control and status registers
6.3.1. Core module ID register, CM_ID
6.3.2. Core module processor register, CM_PROC
6.3.3. Core module oscillator register, CM_OSC
6.3.4. Core module control register, CM_CTRL
6.3.5. Core module statusregister, CM_STAT
6.3.6. Core module lock register,CM_LOCK
6.3.7. Core module bus cycle counter, CM_COUNTER
6.3.8. SDRAM status and controlregister, CM_SDRAM
6.3.9. Core module reference clock cyclecounter, CM_REFCNT
6.3.10. CM flag registers
6.4. CM clock control
6.4.1. Calculating theoutput frequencies of the ICS307
6.4.2. Core Module oscillatorregister, CM_OSC
6.5. CM interrupt control
6.5.1. CM interrupt controller
6.6. CM system bus control
7. CP Image for Operation with an Integrator/CP Baseboard
7.1. About the CP PLD image
7.1.1. Selecting the CP image on a coremodule mounted on an Integrator/CP
7.1.2. CP image functionalblock diagram
7.1.3. The functional block HDL files
7.2. Integrator/CP922T-XA10 system architecture
7.3. Integrator/CP922T memory map
7.4. Integrator/CP922T peripherals and registermemory map
7.5. CM control and status registersfor the CP image
7.5.1. Core module ID register, CM_ID
7.5.2. Core module processor register,CM_PROC
7.5.3. Core module oscillator register,CM_OSC
7.5.4. Core module controland status register for the CP image, CM_CTRL
7.5.5. Core module statusregister, CM_STAT
7.5.6. Core module lockregister, CM_LOCK
7.5.7. Core module auxiliary oscillator register,CM_AUXOSC
7.5.8. SDRAM status andcontrol register, CM_SDRAM
7.5.9. Core module reference clock cyclecounter, CM_REFCNT
7.5.10. CM flag registers
7.6. CP baseboard registers
7.7. Integrator/CP922T system buses
7.7.1. System bus routing and bus interfaces
7.7.2. APB peripheral bus
7.8. Configuring little or big-endian operation
7.9. Integrator/CP922T system memory
7.9.1. Physical locationof memory chips
7.9.2. Baseboard flash memory
7.9.3. Logic module SSRAM
7.10. Integrator/CP922T system clocks
7.10.1. Calculating the output frequenciesof the ICS307
7.10.2. Core module oscillatorregister for the CP image, CM_OSC
7.10.3. Core module auxiliaryoscillator register for the CP image, CM_AUXOSC
7.11. Integrator/CP922T interrupt control
7.11.1. CM interrupt controller
7.11.2. Primary interrupt controller
7.11.3. Secondary interrupt controller
7.11.4. Interrupt routing betweenIntegrator modules
7.11.5. Handling interrupts
8. IM-PD1 Image for Operation with an Integrator/IM-PD1
8.1. About the IM-PD1 image
8.1.1. Selecting the IM-PD1 image
8.1.2. IM-PD1 image functionalblock diagram
8.1.3. The functional block HDL files
8.2. Integrator/CM922T-XA10 and IM-PD1system architecture
8.3. Integrator/CM922T-XA10 and IM-PD1memory map
8.4. Integrator/CM922T-XA10 and IM-PD1register memory map
8.5. CM control and status registersfor the IM-PD1 image
8.5.1. Core module ID register, CM_ID
8.5.2. Core module processor register,CM_PROC
8.5.3. Core module oscillator register,CM_OSC
8.5.4. Core module control register, CM_CTRL
8.5.5. Core module statusregister, CM_STAT
8.5.6. Core module lockregister, CM_LOCK
8.5.7. Core module bus cycle counter,CM_COUNTER
8.5.8. SDRAM status andcontrol register, CM_SDRAM
8.5.9. Core module reference clock cyclecounter, CM_REFCNT
8.5.10. CM flag registers
8.6. Integrator/CM922T-XA10 and IM-PD1interrupt control
8.6.1. Interrupt architecture
8.6.2. CM interrupt controller
8.6.3. Vectored interrupt controller
8.7. IntegratorCM922T-XA10 and IM-PD1clock control
8.7.1. Calculating theoutput frequencies of the ICS307
8.7.2. Core Module oscillatorregister for the IM-PD1 image, CM_OSC
8.8. IM-PD1 registers
8.8.1. Control register, LM_CONTROL
8.9. IM-PD1 Interfaces
8.9.1. Peripheral information block
8.9.2. UART interface
8.9.3. IrDA interface
8.9.4. Smart card interface
8.9.5. USB interface
8.9.6. Audio CODEC
8.9.7. MMC interface
8.9.8. Display interface
8.9.9. Touchscreen controller
A. Signal Descriptions
A.1. HDRA
A.2. HDRB
A.2.1. HDRB socket pinout
A.2.2. HDRB plug pinout
A.2.3. Through-board signal connections
A.2.4. HDRB signal descriptions
A.3. EXPIM plug and socket
A.3.1. EXPIM signals
A.4. Serial interface connector
A.5. Multi-ICE connector
A.6. Trace connector pinout
B. Excalibur PLD Pinout
B.1. Excalibur XA10 pinlist
C. Mechanical Specification
C.1. Mechanical information
C.1.1. Connector part numbers
Glossary

List of Figures

1.1. Integrator/CM922T-XA10 core modulelayout
1.2. LEDs, links, and switches
2.1. IM-PD1 mounted on the core module
2.2. Core module mounted on an Integrator/CPbaseboard
2.3. Assembled Integrator system
2.4. Mode switch
2.5. Power connector
2.6. Multi-ICE connection to a core module
3.1. JTAG connectors, CONFIG link, and CFGENLED
3.2. JTAG data path
3.3. Excalibur internal JTAG data pathrouting (JSELECT=0)
3.4. JTAG clock path
3.5. Trace connection
3.6. Basic tool flow
4.1. Integrator/CM922T-XA10 board architecture
4.2. Altera Excalibur embedded processorPLD
4.3. Embedded processor stripe internalarchitecture
4.4. PLD configuration architecture
4.5. Integrator system bus routing
4.6. Signal rotation scheme
4.7. Flash memory architecture
4.8. Flash memory EBI0 usage
4.9. DDR SDRAM block diagram
4.10. PLD/memory interface signals
4.11. Clocking architecture
4.12. Clock generator control interfacetiming
4.13. Clock control word
4.14. Reset architecture
4.15. Interrupt control
5.1. PLD Basic example image
5.2. Basic example image memory map
5.3. BE_ID register
5.4. BE_LEDs register
6.1. Core module image architecture
6.2. CM image memory map
6.3. CM_ID register
6.4. CM_CTRL register for the CM image
6.5. CM_STAT register
6.6. CM_LOCK register
6.7. CM_SDRAM register
6.8. CM_OSC register
6.9. CM image interrupt control (showingIRQs only)
6.10. Interrupt control
7.1. CP image architecture
7.2. Integrator/CP922T-XA10 system architecture
7.3. CM_ID register
7.4. CM_CTRL register for the CP image
7.5. CM_STAT register
7.6. CM_LOCK register
7.7. CM_SDRAM register
7.8. Bus routing
7.9. Physical memory locations
7.10. Integrator/CP922T clock architecture
7.11. CM_OSC register for the CP image
7.12. CM_AUXOSC register for the CP image
7.13. Interrupt architecture (CP image)
7.14. Interrupt control
7.15. Interrupt signal routing
8.1. IM-PD1 image architecture
8.2. Integrator/CP922T-XA10 systemarchitecture
8.3. CM_ID register
8.4. CM_CTRL register for the IM-PD1 image
8.5. CM_STAT register
8.6. CM_LOCK register
8.7. CM_SDRAM register
8.8. Interrupt architecture (IM-PD1image)
8.9. Interrupt control
8.10. CM_OSC register
A.1. HDRA plug pin numbering
A.2. HDRB socket pin numbering
A.3. HDRB plug pin numbering
A.4. EXPIM plug pin numbering
A.5. Serial interface connector (J1)
A.6. Multi-ICE connector pinout
C.1. Board dimensions

List of Tables

1.1. Core module connectors
1.2. LED functional summary
2.1. Mode switch settings
2.2. General purpose/boot code switch settings
2.3. Boot switcher actions
3.1. Link positions
3.2. JTAG and associated signal description
4.1. Excalibur memory map for the CM image
4.2. Image selection using the mode switch
4.3. Image selection using CFGSEL[1:0]
4.4. System bus connector signal assignments for AHB
4.5. Core module address decode
4.6. General purpose/startup code switch settings
4.7. Assignment of DIMM_DQ signals to SSRAM
4.8. Clock signal usage
4.9. Reset signal descriptions
4.10. Assignment of interrupts for the PLD images
4.11. Interrupt sources
5.1. Basic example image functional block HDL file descriptions
5.2. Basic example image memory map
5.3. Basic example image registers
5.4. BE_ID register bit descriptions
5.5. BE_RST register bit descriptions
5.6. BE_OSCx registers
6.1. CM image functional block HDL file descriptions
6.2. CM image memory map
6.3. Core module status, control, and interrupt registers
6.4. CM_ID register bit descriptions
6.5. CM_CTRL register
6.6. CM_STAT register
6.7. CM_LOCK register
6.8. CM_SDRAM register
6.9. CM_OSC register
6.10. Clock signal association
6.11. CM image interrupt assignment
6.12. Comms interrupt controller registers
6.13. IRQ and FIQ register bit assignment
6.14. IRQ register bit assignment
7.1. CM image functional block HDL file descriptions
7.2. Integrator/CP922T memory map
7.3. Integrator/CP922T system register map
7.4. Core module status, control, and interrupt registers
7.5. CM_ID register bit descriptions
7.6. CM_CTRL register
7.7. CM_STAT register
7.8. CM_LOCK register
7.9. CM_SDRAM register
7.10. CP registers
7.11. Calculating the clock frequencies for the CP image
7.12. CM_OSC register for the CP image
7.13. CM_AUXOSC register for the CP image
7.14. CP image interrupt assignment
7.15. Comms interrupt controller registers
7.16. IRQ and FIQ register bit assignment
7.17. IRQ register bit assignment
7.18. Primary interrupt registers
7.19. Primary interrupt register bit assignments
8.1. VHDL file descriptions
8.2. Integrator/CM922T-XA10 and IM-PD1 memory map
8.3. Integrator/CM922T-XA10 and IM-PD1 system register map
8.4. Core module status, control, and interrupt registers
8.5. CM_ID register bit descriptions
8.6. CM_CTRL register
8.7. CM_STAT register
8.8. CM_LOCK register
8.9. CM_SDRAM register
8.10. IM-PD1 image interrupt assignment
8.11. Comms interrupt controller registers
8.12. IRQ and FIQ register bit assignment
8.13. IRQ register bit assignment
8.14. CM_OSC register
8.15. Clock signal association
8.16. LM registers for the IM-PD1 image
8.17. LM_CONTROL register
A.1. Bus bit assignment (for an AMBA AHB bus)
A.2. Signal cross-connections (example)
A.3. HDRB signal description (AHB)
A.4. Signal differences between EXPIM socket and plug
A.5. Serial interface signal assignment
A.6. Trace connector pinout
B.1. Signal assignments to Excalibur XA10 pins
C.1. Samtec connector part numbers

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt frompart 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Integrator generates, uses, and can radiate radio frequencyenergy and may cause harmful interference to radio communications.However, there is no guarantee that interference will not occurin a particular installation. If this equipment causes harmful interferenceto radio or television reception, which can be determined by turningthe equipment off or on, you are encouraged to try to correct theinterference by one or more of the following measures:

  • ensure attached cables donot lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment andthe receiver

  • connect the equipment into an outlet on a circuitdifferent from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technicianfor help

Note

It is recommended that wherever possible Shielded interfacecables be used.

Revision History
Revision A September2002 First release
Revision B November2003 Second release, updated register information
Copyright © 2002-2003. All rights reserved. ARM DUI 0184B
Non-Confidential