| TP1 | CLK_GLOBAL_IN | Buffered version of global clock signal. This
is fed to a GCLK input of the
FPGA. |
| TP2 | CLK_GLOBAL_OUT | Buffered version of global clock signal from
the FPGA. (This signal is driven even if CLK_GLOBAL_OUT is
disabled.) |
| TP3 | CLK_24MHZ | Buffered replica of the fixed-frequency reference
clock signal that feeds CLK_24MHZ_FPGA and CLK_24MHZ_PLD. |
| TP8 | CLK_OUT | Buffered version of clock signal CLK_OUT_TO_BUF that drives the buffers
for the dual/differential clocking scheme: CLK_OUT_PLUS1 CLK_OUT_PLUS2 CLK_OUT_MINUS1 CLK_OUT_MINUS2 CLK_BUF_LOOP.
|
| TP9 | CLK_SCLK | Buffered version of serial data input clock to
programmable oscillators |
| J7 | DXP and DXN | Temperature sensing diode output. (There is
not a socket fitted to the board, but you can fit a socket or measure
the voltage directly from the socket pads.) |
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