3.2.1. Variable I/O levels
All HDRZ connector signals are fixed at 3.3V I/O signalling
level.
The XU, XL, YU, and YL I/O signalling levels are set to 3.3V
by 0Ω links on the tile. You can however, remove the links and enable
the VCCO blade of a corresponding connector on a plugged-in board
to set the signal level. The signal levels for the FPGA banks are
listed in Table 3.1. (All
ARM Logic Tiles operate at 3.3 volt signal level, but custom tiles
might use a different signal level and supply the voltage to the
VCCO blade.)
Table 3.1. I/O signalling levels
| Bank | VCCO Voltage | Destination | Description |
|---|
| 0 | 3.3V | HDRZ and onboard signals | Fixed |
| 1 | 3.3V | HDRZ and onboard signals | Fixed |
| 2 | 3.3V default | XU signals | Variable, remove R13 to power from tile above |
| 3 | 3.3V default | XL signals | Variable, remove R14 to power from tile below |
| 4 | 3.3V | HDRZ and onboard signals | Fixed |
| 5 | 3.3V | HDRZ and onboard signals | Fixed |
| 6 | 3.3V default | YL signals | Variable, remove R12 to power from tile below |
| 7 | 3.3V default | YU signals | Variable, remove R11 to power from tile above |
Caution
If you provide VCCO from an adjacent tile, you must remove
the relevant 0Ω resistor.
If you require any configuration resistor to be removed or
changed, it is recommended that the work be carried out by a skilled
technician with experience in circuit board soldering. If any board
malfunction is proved as a result of any modification to the board or
components, this immediately invalidates the warranty and could
lead to costs from ARM for repair or replacement.
All pins on the lower HDRX and HDRY connectors must operate
at 3.3V signal levels if the tile is used with a Versatile/PB926EJ-S or an
Integrator motherboard.
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