Three programmable (6 – 200 MHz) clocks are supplied to the I/O pins by three serially programmable MicroClock ICS307 clock generators, as shown in Figure 3.4. These are general purpose clock sources and can be used for your design.
The oscillators also provide the fixed-frequency 24MHz clocks CLK_24MHZ_FPGA and CLK_24MHZ_PLD.
The ICS307s are supplied with a reference clock by a 24MHz crystal oscillator. The frequency of the outputs from the ICS307s are controlled by values loaded into the serial data pins. This enables them to produce a wide range of frequencies. See the manufacturer’s web site for more information.
The frequency of the clock from an ICS307 is set by loading values for the divider and multiplier registers into the serial input port on the clock generator. These control the value of the parameters used to determine the output of the ICS307.
Note
CLK1 and CLK2 in the text below refers to the signals on the ICS307 data sheet, not to CLK1 and CLK2 on the Logic Tile. For the Logic Tile, CLK1 outputs from the ICS307 provide the system clocks and the CLK2 outputs are set to output the 24MHz reference frequency.
You can calculate the frequency using the formula:
where:
- VDW
Is the VCO divider word (4 – 511).
- RDW
Is the reference divider word (1 – 127).
- DIVIDE
Is the divide ratio (2 to 10) selected by the OD bits.
The configuration data stream from the FPGA is shown in Figure 3.5 where:
- C[1:0]
Internal load capacitance for crystal. If you use an external clock, set C[1:0] to
10. See the ICS data sheet for details of capacitance values.- T
Duty cycle threshold setting:
0 selects 1.4V as duty-cycle reference point
1 selects VDD/2 as duty-cycle reference point.
- F[1:0]
Function of CLK2 output:
00 selects reference signal
Note
This must be set for OSC0 and OSC1 and is recommended for OSC2.
01 selects reference signal divided by two
10 disables output for CLK2
11 selects CLK1 signal divided by two.
- S[2:0]
Output divider select (OD).
- V[8:0]
VCO divider word (VDW).
- R[6:0]
Reference divider word (RDW).
Note
Bit 23 is loaded into the shift register first and bit 0 is loaded last. Data is clocked into the register on the rising edge of SCLK. The STROBE signal is pulsed HIGH after all bits have been shifted into the register.
For more information on the ICS clock generator and a frequency
calculator, see the ICS web site at www.icst.com.
Serial control of the programmable clocks must be implemented in the FPGA design. Example HDL (APBClocks and APBClockArbiter) is provided on the CD. (See the examples provided on the CD.)
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