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The configuration flash contains two images that enable the FPGA to be configured at power-on reset. The configuration switches and the global configuration signal controls the image selection.
The image load sequence consists of:
the PLD reading the FPGA_IMAGE signal and the SEL1 and SEL2 signals (DIP switch S2[2:1]) and selecting the lower or upper flash image accordingly (see Configuring the FPGA from flash for details)
setting the IMAGE_LED signal to indicate which image is selected for the FPGA
bytestreaming the flash image into the FPGA
setting the DONELED signal LOW after the FPGA is configured with an image.
Figure 4.1 shows the FPGA configuration mechanism. (For more details see Configuring the FPGA from flash.)
| Copyright © 2002-2007. All rights reserved. | ARM DUI 0186E |
| Non-Confidential | |
| PDF version | |
| Home > Configuring the FPGA and PLD > Configuration system architecture > PLD bytestreamer operation |