The LT-XC2V4000+ Logic Tile is designed as a platform for developing Advanced Microcontroller Bus Architecture (AMBA™) Advanced System Bus (ASB), Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI) peripherals, or custom logic for use with ARM cores.
Note
The Logic Tile must be used with an external board that provides power and Multi-ICE® connectors (for example, the Versatile/PB926EJ-S or the Integrator/IM-LT1 Interface Module).
Some examples of how the Logic Tile can be used are:
For peripheral development or multi-processor development with a Versatile/PB926EJ-S baseboard. The Logic Tile can be used to hold custom peripherals or an implementation of a synthesizable core. Use the Versatile/IT1 Interface Tile for access to the peripheral signals in the Logic Tile.
As a standalone system (together with an interface module such as the Integrator/IM-LT1 provides the power and JTAG connection). Implement a processor in the Logic Tile FPGA or use a Core Tile.
For peripheral development with a motherboard (such as the Integrator/AP or Integrator/CP), an Integrator/IM-LT1 Interface Module, and a core module. (If a synthesized processor core is implemented in the Logic Tile FPGA, the core module is not required.)
Figure 1.1 shows the layout of the Logic Tile.
The LT-XC2V4000+ can be supplied fitted with different Xilinx FPGAs:
- XC2V4000
Contains a Xilinx XC2V4000 FPGA.
- XC2V6000
Contains a Xilinx XC2V6000 FPGA.
- XC2V8000
Contains a Xilinx XC2V8000 FPGA.
The functionality of the Logic Tile is defined by a configuration image loaded into the FPGA at power-up. Two FPGA configuration examples are preloaded into flash (one standalone design and one AMBA AHB slave design).
You can also download your own configurations to flash using Multi-ICE. It is also possible to load an image directly to the FPGA (with either Multi-ICE or JTAG tools supported by the FPGA manufacturer) but directly loaded images are lost when power is removed (see Reconfiguring the FPGA directly).
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