Figure 1.2 shows the architecture of the Logic Tile.
The Logic Tile comprises the following:
Xilinx Virtex II FPGA
configuration Programmable Logic Device (PLD) and flash memory for storing FPGA configurations
Two 2MB ZBT SSRAM chips (these can be used, for example, to model IRAM and DRAM for an ARM core)
clock generators and reset sources
switches
LEDs
battery for DES encryption keys
connectors to other tiles.
These components are described in Chapter 3 Hardware Description.
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