The Logic Tile has several reset signals (most are inputs from the Interface Module or baseboard). Figure 3.13 shows the power-on reset sequence. Figure 3.12 shows the architecture of the reset system. Table 3.6 describes the global reset signals.
Note
You can use the reconfigure pushbutton on the Interface Module or Versatile/PB926EJ-S to reload the FPGA image without resetting the entire system. See the Integrator/IM-LT1 User Guide or the Versatile Platform Baseboard for ARM926EJ-S User Guide for details.
Note
The release time for GLOBAL_DONE depends on other boards in the system. It might be held low longer if other boards take longer to configure.
Table 3.6. Reset signal descriptions
Name | Description | Function |
|---|---|---|
| nPORESET | Power-on reset | This signal generates the D_nTRST pulse at power on. |
nSRST | System reset | nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when you have reset a board. When the signal is driven LOW by the reset controller on the tile, the motherboard resets the whole system by driving nSYSRST LOW. This is also used in configuration mode to control the initialization pin (nINIT) on the FPGAs. Though not a JTAG signal, nSRST is described because it can be controlled by JTAG equipment. NotenSRST splits into two signals, D_nSRST and C_nSRST, to provide the debug and configuration signals on HDRZ. |
nSYSRST | System reset | A system-wide, master reset signal from the platform board (for example the Integrator/AP and IM-LT1). This signal is typically used to reset ARM cores, peripherals and user logic. Can be activated from several sources, including GLOBAL_DONE=0. (See the Integrator/AP Motherboard User Guide or the Integrator/IM-LT1 Interface Module User Guide for more information on motherboard signals.) |
FPGA_nPROG | Configuration reload | The FPGA_nPROG signal forces all FPGAs in the system to reconfigure. |
GLOBAL_DONE | Configuration done | Open-collector signal that goes HIGH when all FPGAs have finished configuring. The system is held in reset until this signal goes HIGH. |
nSYSPOR | Power-on reset | This is a post-configuration reset signal that is passed to all Logic Tiles in a stack. It is generated by analogue circuitry on the IM-LT1/2 Interface Module. It can be used to reset user logic if required. It remains active for between 1 and 10µS after GLOBAL_DONE goes HIGH. |
D_nTRST | TAP controller reset | A system-wide, open collector signal that can be driven LOW by Multi-ICE. This is the debug version of the nTRST signal. It connects to an FPGA input/output pin to provide a reset input to the virtual TAP controller. There are two possible sources of the D_nTRST signal:
|
D_nSRST | Multi-ICE system reset | A system-wide, open collector signal that can be driven LOW by Multi-ICE. This is the debug version of the nSRST signal. |
C_nTRST | TAP controller reset | An open-collector signal that can be driven LOW by Multi-ICE when using the Progcards utility to program the FPGA. (This signal connects to the PROG pin of the FPGA.) This is the config version of the nTRST signal. |
C_nSRST | Multi-ICE system reset | A system-wide, open-collector signal. The IM-LT1/2 shorts this signal to D_nSRST. This signal can be driven LOW by Multi-ICE when using the Progcards utility to program the FPGA. (This signal connects to the INIT pin of the FPGA.) This is the config version of the nSRST signal. NoteOn the Integrator/AP, the expansion connector (EXPB) nSRST signal is completely separate from the core module (HDRB) nSRST signal (see the Integrator/AP User Guide for more details). |
nSETUPRESET | Configuration control | This signal is an output from the PLD indicating to the FPGA that serial foldover configuration transfers can begin. |
PDF version