In debug mode, the FPGA uses the slave select map mode configuration method. In this mode, CCLK is an input to the FPGA and is driven by the configuration PLD. The FPGA configuration is loaded from flash memory and the process is managed by the configuration PLD. The flash must contain valid configuration data and the CONFIG link must not be fitted.

The flash memory can store two FPGA configuration images. The image is selected either by the DIP switch S2 or by the FPGA_IMAGE signal from the IM-LT1 Interface Module or a motherboard (see Configuring the FPGA from flash).