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The following changes were made in RVCT v2.2:
RVCT v2.2 supports the new Thumb®-2 instruction set. Thumb-2 introduces many new 32-bit instructions, and some new 16-bit instructions. Thumb-2 gives near ARM performance together with code size that is similar to the original Thumb on those processors that support it, such as the ARM1156T2(F)-S.
The Thumb-2 instruction set includes older 16-bit Thumb instructions as a subset.
RVCT v2.2 includes support for new ARMv6 cores, for example, the ARM1176JZ(F)-S, incorporating ARM TrustZone™ technology-optimized software, the ARM968EJ-S, the ARM1156T2(F)-S, and the ARM MPCore™.
The RVCT v2.2 assembler provides support for MPCore instructions.
RVCT v2.2 includes support for a new assembler syntax, while continuing to support the old syntax to enable the assembly of legacy code.
RVCT v2.2 is fully compliant with the Base Platform ABI for the ARM Architecture [BPABI], so giving support for a range of operating systems, for example, ARM Linux and Symbian OS.
RVCT v2.2 provides initial support for DWARF 3 (Draft
Standard 9) debug tables, as described in the ABI for
the ARM Architecture (base standard) [BSABI]. A new
command-line option, --dwarf3, is now available
to specify this format when compiling code.
The command-line option --debug or -g switches
on the generation of debug tables for the current compilation. Optimization
options are specified by -O. By
default, using the num--debug or -g option
does not affect the optimization setting.
This is a change in behavior for RVCT v2.2 (--debug or -g alone
was equivalent to [--debug|-g] -O0 in RVCT v2.1). Apart
from this new default, there is no change in the behavior of the
optimization options, that is, -O, num-Ospace,
or -Otime.
RVCT v2.2 supports the command-line option --apcs
/fpic to compile code that is compatible with System V
shared libraries. Use this option to generate read-only position-independent
code where relative address references are independent of the location
where your program is loaded.
The ARM linker supports building, and linking against, shared libraries. New command-line options are available to build SVr4 executable files and shared objects, and to specify how code is generated.
The ARM linker conforms to the Base Platform ABI for the ARM Architecture [BPABI] and supports the GNU-extended symbol versioning model.
The ARM implementation of floating-point computations has been changed to provide improved support for C99 functions. Where this changes behavior significantly, a compatibility mode has been introduced to aid developers to migrate code to use the new features. See Changes to library support for more information.
The ARM compiler C implementation has been changed so that it now issues a Warning for out-of-range enumerator values. Such values are treated the same way as in C++. This means the size of enum types with out-of-range values might be different in C when you upgrade to the latest release of RVCT.
There is no change if you are using C++, or the command-line
options --enum_is_int, --strict,
or --strict_warnings. See Changes to the ARM compiler for more information.
The ARM libraries have been enhanced to provide improved support for multithreading. This is designed to help developers who are working with RTOS-based systems.
The ARM compiler offers new options to provide greater control of how dynamic symbols are exported:
--dllexport_all
--no_hide_all.
The ARM linker can perform some branch optimizations that are not available to other components of RVCT. Two new command-line options are available to handle tail calling sections to optimize the branch instruction at the end of the section.
Options that were deprecated in RVCT v2.1 are now obsolete in v2.2 (see Obsolete features).
Some options that were supported in RVCT v2.1 are now deprecated in v2.2 (see Deprecated features).
The following changes were made in RVCT v2.2:
All features and options that were deprecated in RVCT v2.1 are obsolete in RVCT v2.2, that is:
Legacy Software Development Toolkit (SDT) formats such as ARM Object Format (AOF) and libraries in ARM Library Format (ALF) format.
The use of single dashes for keywords, for example, armlink
-help.
The compiler options -ansi and -ansic.
Old compiler option names that were deprecated in
RVCT v2.1 are obsolete in RVCT v2.2, for example, -fy, -fd, -Ec,
and -zo,
The compiler issues a warning where a preferred option name exists, for example:
armcc -zo
Warning: X0010W: Old syntax, please use '--split_sections'.
See Appendix E in RealView Compilation Tools v3.0 Compiler and Libraries Guidefor a list.
Selected older ARM processors and architectures are obsolete:
ARM6
ARMv3 and ARMv3M.
To see a full list of supported cores use:
armcc --cpu list
Selected older floating-point architectures are obsolete:
VFPv1 (the default is VFPv2)
FPA
Soft FPA.
Unless specified, the default is Soft VFP.
To see a full list of supported floating-point architectures use:
armcc --fpu list
The following compiler options are obsolete:
--fpu fpa, --fpu
softfpa, and --fpu vfpv1
--fa
--cpu 3 and --cpu 3M
-Oldrd and -Ono_ldrd
-W and letter-E.letter
Synonyms for the SXT and UXT instructions
(sign extend or zero extend) are not supported.
Use of FPA registers f0-f7 and F0-F7 is
obsolete.
The use of the environment variable RVCT21_CLWARN to
warn against deprecated options is not supported.
The following changes were made in RVCT v2.2:
The compiler supports the option --apcs
/adsabi to compile code that is compatible with the old ARM Developer Suite™ (ADS) Application
Binary Interface (ABI). This is deprecated and will be
removed in a future release.
The ARM linker and fromelf accept
two forms of negated option, for example, --no_debug and --nodebug.
However, the non-standard form, for example, --nodebug,
is deprecated and will not be supported in the future. A warning
is issued if you use the deprecated syntax.
The C++ configuration option --dll_vtbl has
been replaced by the new option --export_all_vtbl.
The option --dll_vtbl is deprecated and will not
be supported in the future.
The RVCT assembler supports two forms of the Load Register EXclusive instruction:
LDREX{B|D|H}{cond} Rd, [Rn]
LDR{B|D|H}EX{cond} Rd, [Rn]
The second is deprecated and will be removed in a future release.
The disassembler supports only the first form.
The RVCT assembler supports two forms of the Store Register EXclusive instruction:
STREX{B|D|H}{cond} Rd, [Rn]
STR{B|D|H}EX{cond} Rd, [Rn]
The second is deprecated and will be removed in a future release.
The disassembler supports only the first form.