7.3.1. Comms data control register

The following instruction returns the control register value in Rd:

    MRC p14, 0, Rd, c0, c0

Two bits in this control register provide synchronized handshaking between the target and the host debugger:

Bit 1 (W bit)

Denotes whether the comms data write register is free (from the target point of view):

W = 0

New data can be written by the target application.

W = 1

The host debugger can scan new data out of the write register.

Bit 0 (R bit)

Denotes whether there is new data in the comms data read register (from the target point of view):

R = 1

New data is available to be read by the target application.

R = 0

The host debugger can scan new data into the read register.


The debugger cannot use coprocessor 14 to access the debug communications channel directly, because this has no meaning to the debugger. Instead, the debugger can read from and write to the DCC registers using the scan chain. The DCC data and control registers are mapped into addresses in the EmbeddedICE logic. To view the EmbeddedICE logic registers, see the documentation for your debugger and debug target.

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