1.2. General programming issues

ARM processors are Reduced Instruction Set Computing (RISC) processors and many of the programming strategies that give efficient code are generic to this type of device.

As with many RISC processors, ARM processors are designed to access aligned data, that is, words that lie on addresses that are multiples of four, and halfwords that lie on addresses that are multiples of two. This data is located on its natural size boundary.

ARM compilers normally align global variables to these natural size boundaries so that these items can be accessed efficiently using the LDR and STR instructions.

This contrasts with most Complex Instruction Set Computing (CISC) architectures where instructions are available to directly access unaligned data. Therefore, you must take care when porting legacy code from CISC architectures to the ARM processors. In particular, accesses to unaligned data can be expensive in code size or performance.


ARM11 processors support unaligned accesses in hardware. This section mainly applies to ARM processors earlier than the ARM11 processor family.

The following sections discuss these programming issues in more detail:

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