6.3.1. The processor response to an exception

When an exception is generated, the processor performs the following actions:

  1. Copies the Current Program Status Register (CPSR) into the Saved Program Status Register (SPSR) for the mode in which the exception is to be handled. This saves the current mode, interrupt mask, and condition flags.

  2. Switches to ARM state, if it is currently in Thumb state.

  3. Changes the appropriate CPSR mode bits in order to:

    • change to the appropriate mode, and map in the appropriate banked registers for that mode

    • disable interrupts. IRQs are disabled when any exception occurs. FIQs are disabled when a FIQ occurs and on reset.

  4. Sets lr_mode to the return address, as defined in The return address and return instruction.

  5. Sets the PC to the vector address for the exception.

    For ARM processors that do not support Thumb, this forces a branch to the appropriate exception handler.

    For processors that support Thumb, the switch from Thumb state to ARM state in step 2 ensures that the ARM instruction installed at this vector address (either a branch or a PC-relative load) is correctly fetched, decoded, and executed. This forces a branch to a top-level veneer that you must write in ARM code.

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