1.4.1. Instruction generation

When compiling code for ARMv6, the compiler generates sign-extend and zero-extend instructions (for example, SEXT8), where appropriate (see Example 1 - Sign/Zero extension). Code scheduling for the specified processor is performed.

In addition, the C libraries contain some functions that are optimized specifically for ARMv6, such as memcpy(), memove(), and strcmp().

The compiler does not make use of SIMD instructions, because these do not map well onto C expressions. The endian reversal instructions (REV, REV16 and REVSH) are generated by the compiler if it can deduce that a C expression performs an endian reversal.

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