6.1.1. Types of exception

Table 6.1 shows the different types of exception recognized by ARM processors.

Table 6.1. Exception types

ExceptionDescription
ResetOccurs when the processor reset pin is asserted. This exception is only expected to occur for signaling power-up, or for resetting as if the processor has powered up. A soft reset can be done by branching to the reset vector (0x0000).
Undefined InstructionOccurs if neither the processor, nor any attached coprocessor, recognizes the currently executing instruction.
Supervisor Call (SVC)This is a user-defined synchronous interrupt instruction. It enables a program running in User mode, for example, to request privileged operations that run in Supervisor mode, such as an RTOS function.
Prefetch AbortOccurs when the processor attempts to execute an instruction that was not fetched, because the address was illegal (see Illegal addresses).
Data AbortOccurs when a data transfer instruction attempts to load or store data at an illegal address (see Illegal addresses).
IRQOccurs when the processor external interrupt request pin is asserted (LOW) and the I bit in the CPSR is clear.
FIQOccurs when the processor external fast interrupt request pin is asserted (LOW) and the F bit in the CPSR is clear.

Illegal addresses

An illegal virtual address is one that does not currently correspond to an address in physical memory, or one that the memory management subsystem has determined is inaccessible to the processor in its current mode.

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