6.11. Data Abort handler

If there is no MMU, the Data Abort handler must report the error and quit. If there is an MMU, the handler must deal with the virtual memory fault.

The instruction that caused the abort is at lr_ABT-8 because lr_ABT points two instructions beyond the instruction that caused the abort.

The following types of instruction can cause this abort:

Single Register Load or Store (LDR or STR)

The response depends on the processor type:

  • If the abort takes place on an ARM7 processor, including the ARM7TDMI®, the address register has been updated and the change must be undone.

  • If the abort takes place on an ARM9, ARM10, StrongARM, or later processor, the address is restored by the processor to the value it had before the instruction started. No further action is required to undo the change.

Swap (SWP)

There is no address register update involved with this instruction.

Load Multiple or Store Multiple (LDM or STM)

The response depends on the processor type:

  • If the abort takes place on an ARM7 processor, and writeback is enabled, the base register is updated as if the whole transfer had taken place.

    In the case of an LDM with the base register in the register list, the processor replaces the overwritten value with the modified base value so that recovery is possible. The original base address can then be recalculated using the number of registers involved.

  • If the abort takes place on an ARM9, ARM10, StrongARM, or later processor and writeback is enabled, the base register is restored to the value it had before the instruction started.

In each of the three cases the MMU can load the required virtual memory into physical memory. The MMU Fault Address Register (FAR) contains the address that caused the abort. When this is done, the handler can return and try to execute the instruction again.

You can find example Data Abort handler code in the main examples directory, in ...\databort.

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