6.2. Determining the processor state

An exception handler might have to determine whether the processor was in ARM or Thumb® state when the exception occurred.

SVC handlers, especially, might have to read the processor state. This is done by examining the SPSR T-bit. This bit is set for Thumb state and clear for ARM state.

Both ARM and Thumb instruction sets have the SVC instruction. When calling SVCs from Thumb state, you must consider the following:

Figure 6.1. Thumb SVC instruction

Example 6.1 shows ARM code that handles a SVC from both sources.

Consider the following:

Example 6.1. SVC handler

T_bit   EQU    0x20                     ; Thumb bit of CPSR/SPSR, that is,
                                        ; bit 5.
        STMFD   sp!, {r0-r3,r12,lr}     ; Store registers.
        MRS     r0, spsr                ; Move SPSR into
                                        ; general purpose register.
        TST     r0, #T_bit              ; Occurred in Thumb state?
        LDRNEH  r0,[lr,#-2]             ; Yes: load halfword and...
        BICNE   r0,r0,#0xFF00           ; ...extract comment field.
        LDREQ   r0,[lr,#-4]             ; No: load word and...
        BICEQ   r0,r0,#0xFF000000       ; ...extract comment field.

            ; r0 now contains SVC number

        CMP     r0, #MaxSVC             ; Rangecheck
        LDRLS   pc, [pc, r0, LSL#2]     ; Jump to the appropriate routine.
        B       SVCOutOfRange
        DCD     do_svc_1
        DCD     do_svc_2
        ; Handle the SVC.
        LDMFD   sp!, {r0-r3,r12,pc}^   ; Restore the registers and return.
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