RealView® Compilation Tools Developer Guide

Version 3.1


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView Compilation Tools
Feedback on this book
1. Introduction
1.1. About RVCT
1.1.1. Using the examples
1.2. Developing for the ARM processors
1.2.1. Embedded software development
1.2.2. Interworking ARM and Thumb code
1.2.3. Mixing C, C++, and assembly language
1.2.4. Handling processor exceptions
1.2.5. Using the AAPCS
1.2.6. Compatibility with legacy objects and libraries
2. Embedded Software Development
2.1. About embedded software development
2.1.1. Example code
2.2. Default compilation tool behavior in the absence of a target system
2.2.1. Semihosting
2.2.2. C library structure
2.2.3. Default memory map
2.2.4. Linker placement rules
2.2.5. Application startup
2.2.6. Example code for Build 1
2.3. Tailoring the C library to your target hardware
2.3.1. Retargeting the C library
2.3.2. Avoiding C library semihosting
2.3.3. Example code for Build 2
2.4. Tailoring the image memory map to your target hardware
2.4.1. Scatter‑loading
2.4.2. Scatter‑loading description file syntax
2.4.3. Scatter‑loading description file example
2.4.4. Placing objects in a scatter‑loading description file
2.4.5. Root regions
2.4.6. Placing the stack and heap
2.4.7. Runtime memory models
2.4.8. Example code for Build 3
2.4.9. ARMv6-M and ARMv7-M memory maps
2.5. Reset and initialization
2.5.1. Initialization sequence
2.5.2. The vector table
2.5.3. ROM/RAM remapping
2.5.4. Local memory setup considerations
2.5.5. Scatter‑loading and memory setup
2.5.6. Stack pointer initialization
2.5.7. Hardware initialization
2.5.8. Execution mode considerations
2.5.9. Example code for Build 4
2.6. Other memory map considerations
2.6.1. Locating target peripherals in the scatter‑loading description file
2.6.2. Example code for Build 5
3. Writing Position Independent Code and Data
3.1. Position independence
3.1.1. Using the AAPCS
3.2. Read‑only position independence
3.2.1. Register usage with ROPI
3.2.2. Writing C and assembler code for ROPI
3.2.3. Linking your code
3.2.4. FPIC addressing
3.2.5. Code example
3.3. Read‑write position independence
3.3.1. Reentrant routines
3.3.2. Register usage with RWPI
3.3.3. Position‑independent data addressing
3.3.4. Writing assembly language for RWPI
3.3.5. Linking your code
3.3.6. Code example
4. Interworking ARM and Thumb
4.1. About interworking
4.1.1. Using the AAPCS
4.1.2. When to use interworking
4.1.3. Using the /interwork option
4.1.4. Detecting interworking calls
4.1.5. Linker generated veneers
4.2. Assembly language interworking
4.2.1. The branch and exchange instruction
4.2.2. Changing the assembler mode
4.2.3. Example ARM header
4.2.4. Interworking with ARM architecture v5T and later
4.2.5. Labels in Thumb code
4.3. C and C++ interworking and veneers
4.3.1. Compiling code for interworking
4.3.2. Basic rules for C and C++ interworking
4.3.3. Pointers to functions in Thumb state
4.3.4. Using two versions of the same function
4.4. Assembly language interworking using veneers
4.4.1. Assembly‑only interworking using veneers
4.4.2. C, C++, and assembly language interworking using veneers
5. Mixing C, C++, and Assembly Language
5.1. Using the inline and embedded assemblers
5.1.1. Features of the inline assembler
5.1.2. Features of the embedded assembler
5.1.3. Differences between inline and embedded assembly code
5.2. Accessing C global variables from assembly code
5.3. Using C header files from C++
5.3.1. Including system C header files
5.3.2. Including your own C header files
5.4. Calling between C, C++, and ARM assembly language
5.4.1. General rules for calling between languages
5.4.2. Information specific to C++
5.4.3. Examples of calling between languages
6. Handling Processor Exceptions
6.1. About processor exceptions
6.1.1. Types of exception
6.1.2. The vector table
6.1.3. Use of modes and registers by exceptions
6.1.4. Exception priorities
6.2. Determining the processor state
6.3. Entering and leaving an exception
6.3.1. The processor response to an exception
6.3.2. Returning from an exception handler
6.3.3. The return address and return instruction
6.4. Handling an exception
6.5. Installing an exception handler
6.5.1. Methods of installing exception handlers
6.5.2. Installing the handlers at reset
6.5.3. Installing the handlers from C
6.6. SVC handlers
6.6.1. Determining the SVC to be called
6.6.2. SVC handlers in assembly language
6.6.3. SVC handlers in C and assembly language
6.6.4. Using SVCs in Supervisor mode
6.6.5. Calling SVCs from an application
6.6.6. Calling SVCs dynamically from an application
6.7. Interrupt handlers
6.7.1. Levels of external interrupt
6.7.2. Simple interrupt handlers in C
6.7.3. Reentrant interrupt handlers
6.7.4. Example interrupt handlers in assembly language
6.8. Reset handlers
6.9. Undefined Instruction handlers
6.10. Prefetch Abort handler
6.11. Data Abort handler
6.12. System mode
7. Handling Cortex-M3 Processor Exceptions
7.1. About Cortex-M3 processor exceptions
7.1.1. Operating and execution modes
7.1.2. Main and Process Stacks
7.1.3. Exception numbers
7.1.4. The vector table
7.1.5. Events
7.1.6. Exception priorities and pre-emption
7.1.7. The Nested Vectored Interrupt Controller
7.2. Writing the exception table
7.3. Writing the exception handlers
7.4. Placing the exception table
7.5. Configuring the System Control Space registers
7.6. Configuring individual IRQs
7.6.1. Interrupt priorities
7.7. Supervisor calls
7.8. System timer
7.8.1. Configuring SysTick
7.9. Porting exception handling code written for other ARM processors
7.9.1. Critical sections and exception behavior
8. Debug Communications Channel
8.1. About the Debug Communications Channel
8.2. Target transfer of data
8.3. Polled debug communications
8.3.1. Comms data control register
8.3.2. Target to debugger communication
8.3.3. Debugger to target communication
8.4. Interrupt‑driven debug communications
8.5. Access from Thumb state
A. Semihosting
A.1. About semihosting
A.1.1. What is semihosting?
A.1.2. The semihosting interface
A.2. Semihosting implementation
A.2.1. RealView ARMulator ISS
A.2.2. RealView ICE
A.2.3. Instruction Set System Model
A.2.4. RealMonitor
A.3. Semihosting operations
A.3.1. angel_SWIreason_EnterSVC (0x17)
A.3.2. angel_SWIreason_ReportException (0x18)
A.3.3. SYS_CLOSE (0x02)
A.3.4. SYS_CLOCK (0x10)
A.3.5. SYS_ELAPSED (0x30)
A.3.6. SYS_ERRNO (0x13)
A.3.7. SYS_FLEN (0x0C)
A.3.8. SYS_GET_CMDLINE (0x15)
A.3.9. SYS_HEAPINFO (0x16)
A.3.10. SYS_ISERROR (0x08)
A.3.11. SYS_ISTTY (0x09)
A.3.12. SYS_OPEN (0x01)
A.3.13. SYS_READ (0x06)
A.3.14. SYS_READC (0x07)
A.3.15. SYS_REMOVE (0x0E)
A.3.16. SYS_RENAME (0x0F)
A.3.17. SYS_SEEK (0x0A)
A.3.18. SYS_SYSTEM (0x12)
A.3.19. SYS_TICKFREQ (0x31)
A.3.20. SYS_TIME (0x11)
A.3.21. SYS_TMPNAM (0x0D)
A.3.22. SYS_WRITE (0x05)
A.3.23. SYS_WRITEC (0x03)
A.3.24. SYS_WRITE0 (0x04)
A.4. Debug agent interaction SVCs

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AAugust 2002Release 1.2
Revision BJanuary 2003Release 2.0
Revision CSeptember 2003Release 2.0.1 for RVDS v2.0
Revision DJanuary 2004Release 2.1 for RVDS v2.1
Revision EDecember 2004Release 2.2 for RVDS v2.2
Revision FMay 2005Release 2.2 for RVDS v2.2 SP1
Revision GMarch 2006Release 3.0 for RVDS 3.0
Revision HMarch 2007Release 3.1 for RVDS 3.1.
Copyright © 2002-2007 ARM Limited. All rights reserved.ARM DUI 0203H
Non-Confidential