4.11.4. LDR pseudo-instruction

Load a register with either:


This section describes the LDR pseudo-instruction only. See Memory access instructions for information on the LDR instruction.

Also, see Loading with LDR Rd, =const, for information on loading constants with the LDR pseudo-instruction.


LDR{cond}{.w} register,=[expr | label-expr]



is an optional condition code (see Conditional execution).


is an optional instruction width specifier. See LDR in Thumb-2 for details.


is the register to be loaded.


evaluates to a numeric constant:

  • The assembler generates a MOV or MVN instruction, if the value of expr is within range.

  • If the value of expr is not within range of a MOV or MVN instruction, the assembler places the constant in a literal pool and generates a program-relative LDR instruction that reads the constant from the literal pool.


is a program-relative or external expression. The assembler places the value of label-expr in a literal pool and generates a program-relative LDR instruction that loads the value from the literal pool.

If label-expr is an external expression, or is not contained in the current section, the assembler places a linker relocation directive in the object file. The linker generates the address at link time.


The main purposes of the LDR pseudo-instruction are:

  • To generate literal constants when an immediate value cannot be moved into a register because it is out of range of the MOV and MVN instructions

  • To load a program-relative or external address into a register. The address remains valid regardless of where the linker places the ELF section containing the LDR.


    An address loaded in this way is fixed at link time, so the code is not position-independent.

The offset from the PC to the value in the literal pool must be less than ±4KB (ARM, 32-bit Thumb-2) or in the range 0 to +1KB (Thumb, 16-bit Thumb-2). You are responsible for ensuring that there is a literal pool within range. See LTORG for more information.

See Loading constants into registers for a more detailed explanation of how to use LDR, and for more information on MOV and MVN.


This ARM pseudo-instruction is available in all versions of the ARM architecture.

For 32-bit Thumb-2, see LDR in Thumb-2.

This 16-bit Thumb pseudo-instruction is available in all T variants of the ARM architecture.

LDR in Thumb-2

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb-2 code.

LDR.W always generates a 32-bit instruction, even if the constant could be loaded in a 16-bit MOV, or there is a literal pool within reach of a 16-bit pc-relative load.

LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in a 16-bit pc-relative load for a constant that could be generated in a 32-bit MOV or MVN instruction.

You can also use MOV32 (see MOV32 pseudo-instruction). This can place any 32-bit value in a register without a load operation, using two instructions.


        LDR     r3,=0xff0    ; loads 0xff0 into r3
                             ; =>  MOV r3,#0xff0
        LDR     r1,=0xfff    ; loads 0xfff into r1
                             ; =>  LDR r1,[pc,offset_to_litpool]
                             ;     ...
                             ;     litpool DCD 0xfff
        LDR     r2,=place    ; loads the address of
                             ; place into r2
                             ; =>  LDR r2,[pc,offset_to_litpool]
                             ;     ...
                             ;     litpool DCD place
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