### 5.7.9. FMAC, FNMAC, FMSC,
and FNMSC

Floating-point multiply-accumulate, negate-multiply-accumulate,
multiply-subtract and negate-multiply-subtract.

These instructions can be scalar, vector, or mixed (see *Vector and scalar operations*).

<`op`

><`precision`

>{`cond`

} `Fd`

, `Fn`

, `Fm`

where:

`<``op`

>

must be one of `FMAC`

, `FNMAC`

, `FMSC`

,
or `FNMSC`

.

`<``precision`

>

must be either `S`

for single-precision,
or `D`

for double-precision.

`cond`

is an optional condition code (see *VFP and condition codes*).

`Fd`

is the VFP register for the result.

`Fn`

is the VFP register holding the first operand.

`Fm`

is the VFP register holding the second operand.

The precision of `Fd`

, `Fn`

and `Fm`

must
match the precision specified in `<``precision`

>

.

The `FMAC`

instruction calculates `Fd`

+ `Fn`

* `Fm`

and
places the result in `Fd`

.

The `FNMAC`

instruction calculates `Fd`

– `Fn`

* `Fm`

and
places the result in `Fd`

.

The `FMSC`

instruction calculates –`Fd`

+ `Fn`

* `Fm`

and
places the result in `Fd`

.

The `FNMSC`

instruction calculates –`Fd`

– `Fn`

* `Fm`

and
places the result in `Fd`

.

These operations can produce Invalid Operation, Overflow,
Underflow, or Inexact exceptions.

FMACD d8, d0, d8

FMACS s20, s24, s28

FNMSCSLE s6, s0, s26