5.7.8. FLDM and FSTM

Floating-point load multiple and store multiple.


FLDM<addressmode><precision>{cond} Rn,{!} VFPregisters
FSTM<addressmode><precision>{cond} Rn,{!} VFPregisters



must be one of:


meaning Increment address After each transfer.


meaning Decrement address Before each transfer.


meaning Empty Ascending stack operation. This is the same as DB for loads, and the same as IA for saves.


meaning Full Descending stack operation. This is the same as IA for loads, and the same as DB for saves.


must be one of:


for single-precision.


for double-precision.


for unspecified precision.


is an optional condition code (see VFP and condition codes).


is the ARM register holding the base address for the transfer.


is optional. ! specifies that the updated base address must be written back to Rn.


If ! is not specified, <addressmode> must be IA.


is a list of consecutive floating-point registers enclosed in braces, { and }. The list can be comma-separated, or in range format. There must be at least one register in the list.


The FLDM instruction loads several consecutive floating-point registers from memory.

The FSTM instruction saves the contents of several consecutive floating-point registers to memory.

If <precision> is specified as D, VFPregisters must be a list of double-precision registers, and two words are transferred for each register in the list.

If <precision> is specified as S, VFPregisters must be a list of single-precision registers, and one word is transferred for each register in the list.

Unspecified precision

If <precision> is specified as X, VFPregisters must be specified as double-precision registers. However, any or all of the specified double-precision registers can actually contain two single-precision values or integers.

The number of words transferred might be 2n or (2n +1), where n is the number of double-precision registers in the list. This is implementation dependent. However, if writeback is specified, Rn is always adjusted by (2n+1) words.

You must only use unspecified-precision loads and saves in matched pairs, to save and restore data. The format of the saved data is implementation-dependent.


    FLDMIAS r2, {s1-s5}
    FSTMFDD r13!, {d3-d6}
    FSTMIAS r0!, {s31}

The following instructions are equivalent:

    FLDMIAS r7, {s3-s7}
    FLDMIAS r7, {s3,s4,s5,s6,s7}

The following instructions must always be used as a matching pair:

    FSTMFDX r13!, {d0-d3}
    FLDMFDX r13!, {d0-d3}

The following instruction is illegal, as the registers in the list are not consecutive:

    FLDMIAD r13!, {d0,d2,d3}
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