4.2.2. LDR and STR (zero, immediate, or pre-indexed immediate offset)

Load and Store. Byte and halfword loads are zero-extended or sign-extended to 32 bits.

Note

Also, see Pseudo-instructions.

Syntax

op{type}{T}{cond} Rd, {Rd2,} [Rn {, #offset}]{!}

where:

op

can be any one of:

LDR

Load Register

STR

Store Register.

type

can be any one of:

B

unsigned Byte

SB

Signed Byte (LDR only)

H

unsigned Halfword

SH

Signed Halfword (LDR only)

-

omitted, for Word

D

Doubleword.

T

is an optional suffix. If T is present, the memory system treats the access as though the processor was in User mode, even if it is in a privileged mode (see Processor mode). T has no effect in User mode.

cond

is an optional condition code (see Conditional execution).

Rd

is the ARM register to load or save.

Rd2

is the second ARM register to load or save (type == D only).

Rn

is the register on which the memory address is based.

offset

is an immediate offset. If offset is omitted, the instruction is a zero offset instruction.

!

is an optional suffix. If ! is present, the instruction is a pre-indexed instruction, and Rn must not be the same register as Rd or Rd2.

Zero offset

The value in Rn is used as the address for the transfer.

The T suffix is not available for Doubleword instructions.

Immediate offset

The offset is applied to the value in Rn before the data transfer takes place. The result is used as the memory address for the transfer. The range of offsets allowed is:

  • –4095 to +4095 for ARM Word or Byte instructions.

  • –255 to +255 for ARM Signed Byte, Halfword, Signed Halfword, and Doubleword instructions.

  • –255 to +4095 for all Thumb-2 instructions without the T suffix, except Doubleword instructions.

  • –1020 to +1020 for Thumb-2 Doubleword instructions. Must be a multiple of 4.

  • 0 to +255 for Thumb-2 instructions with the T suffix.

The T suffix is not available for ARM instructions, or for Thumb-2 Doubleword instructions. It is available for all other Thumb-2 instructions.

Pre-indexed immediate offset

The offset is applied to the value in Rn before the data transfer takes place. The result is used as the memory address for the transfer. The result is written back into Rn.

The range of offsets allowed is:

  • –4095 to +4095 for ARM Word or Byte instructions.

  • –255 to +255 for ARM Signed Byte, Halfword, Signed Halfword, and Doubleword instructions.

  • –255 to +255 for all Thumb-2 instructions except Doubleword instructions.

  • –1020 to +1020 for Thumb-2 Doubleword instructions. Must be a multiple of 4.

The T suffix is not available for ARM instructions or Thumb-2 instructions.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify r15 for either Rd or Rd2.

For ARM instructions:

  • Rd must be an even-numbered register

  • Rd must not be r14

  • Rd2 must be R(d + 1).

16-bit instructions

16-bit versions of a subset of these instructions are available in Thumb-2 code, and in Thumb code on other Thumb-capable processors.

The following restrictions apply to 16-bit instructions:

  • Only zero offset and immediate offset instructions are available. Pre-indexed immediate offset instructions are not available.

  • Use of the T suffix is not allowed.

  • If Rn is not r13:

    • Rd and Rn must both be Lo registers

    • for a Word instruction, offset must be in the range 0 to +124, and must be divisible by 4

    • for a Halfword instruction, offset must be in the range 0 to +62, and must be divisible by 2

    • for a Byte instruction, offset must be in the range 0 to +31

    • Signed Byte, Signed Halfword, and Doubleword instructions are not available.

  • If Rn is r13:

    • Rd must be a Lo register

    • the instruction must be a Word instruction

    • offset must be in the range 0 to +1020, and must be divisible by 4.

Loading to r15

Rd can be the PC, in either ARM or Thumb-2 code. In this case, type must be omitted.

A load to r15 (pc) causes a branch to the instruction at the address loaded.

In ARMv4, bits[1:0] of the value loaded must be zero.

In ARMv5 and above:

  • bits[1:0] of a value loaded to r15 must not have the value 0b10

  • if bit[0] of a value loaded to r15 is set, the processor changes to Thumb state.

You cannot use the T suffix when loading to r15.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in all T2 variants of the ARM architecture.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

In T and T2 variants of ARMv5 and above:

  • in ARM state, a load to r15 causes a change to Thumb state if bit[0] of the value loaded is 1

  • in Thumb state, a load to r15 causes a change to ARM state if bit[0] of the value loaded is 0.

Examples

    LDR     r8,[r10]            ; loads r8 from the address in r10.

    LDRNE   r2,[r5,#960]!       ; (conditionally) loads r2 from a word
                                ; 960 bytes above the address in r5, and
                                ; increments r5 by 960.

    STR     r2,[r9,#consta-struc]   ; consta-struc is an expression evaluating
                                    ; to a constant in the range 0-4095.

    STR     r5,[r7],#-8         ; stores a word from r5 to the address
                                ; in r7, and then decrements r7 by 8.

    LDR     r0,localdata        ; loads a word located at label localdata
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